Issued Patents All Time
Showing 26–50 of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6815968 | Reduced terminal testing system | Warren M. Farnworth, Leland R. Nevill, Raymond J. Beffa | 2004-11-09 |
| 6809985 | DRAM technology compatible processor/memory chips | Leonard Forbes, Wendell P. Noble | 2004-10-26 |
| 6756576 | Imaging system having redundant pixel groupings | David J. McElroy | 2004-06-29 |
| 6741519 | DRAM technology compatible processor/memory chips | Leonard Forbes, Wendell P. Noble | 2004-05-25 |
| 6700821 | Programmable mosfet technology and programmable address decode and correction | Leonard Forbes, Wendell P. Noble | 2004-03-02 |
| 6636068 | Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer | Warren M. Farnworth, William K. Waller, Leland R. Nevill, Raymond J. Beffa | 2003-10-21 |
| 6622224 | Internal buffered bus for a drum | — | 2003-09-16 |
| 6586835 | Compact system module with built-in thermoelectric cooling | Kie Y. Ahn, Leonard Forbes | 2003-07-01 |
| 6570248 | Structure and method for a high-performance electronic packaging assembly | Kie Y. Ahn, Leonard Forbes | 2003-05-27 |
| 6555399 | Double-packaged multichip semiconductor module | Alan G. Wood, Larry D. Kinsman | 2003-04-29 |
| 6535393 | Electrical device allowing for increased device densities | Salman Akram, Warren M. Farnworth, Alan G. Wood, J. Michael Brooks | 2003-03-18 |
| 6534785 | Reduced terminal testing system | Warren M. Farnworth, Leland R. Nevill, Raymond J. Beffa | 2003-03-18 |
| 6525413 | Die to die connection method and assemblies and packages including dice so connected | Paul A. Farrar | 2003-02-25 |
| 6521958 | MOSFET technology for programmable address decode and correction | Leonard Forbes, Wendell P. Noble | 2003-02-18 |
| 6498739 | Applications for non-volatile memory cells | Wendell P. Noble | 2002-12-24 |
| 6477662 | Apparatus and method implementing repairs on a memory device | Ray Beffa, William K. Waller, Lee R. Nevill, Warren M. Farnworth | 2002-11-05 |
| 6456535 | Dynamic flash memory cells with ultra thin tunnel oxides | Leonard Forbes, Luan C. Tran, Alan R. Reinberg, Joseph E. Geusic, Kie Y. Ahn +2 more | 2002-09-24 |
| 6452415 | Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer | Warren M. Farnworth, William K. Waller, Leland R. Nevill, Raymond J. Beffa | 2002-09-17 |
| 6452856 | DRAM technology compatible processor/memory chips | Leonard Forbes, Wendell P. Noble | 2002-09-17 |
| 6424168 | Reduced terminal testing system | Warren M. Farnworth, Leland R. Nevill, Raymond J. Beffa | 2002-07-23 |
| 6380581 | DRAM technology compatible non volatile memory cells with capacitors connected to the gates of the transistors | Wendell P. Noble | 2002-04-30 |
| 6373740 | Transmission lines for CMOS integrated circuits | Leonard Forbes, Kie Y. Ahn | 2002-04-16 |
| 6356500 | Reduced power DRAM device and method | Kie Y. Ahn, Leonard Forbes, Paul A. Farrar, Kevin G. Donohoe, Alan R. Reinberg +3 more | 2002-03-12 |
| 6319773 | Construction and application for non-volatile, reprogrammable switches | Wendell P. Noble | 2001-11-20 |
| 6313658 | Device and method for isolating a short-circuited integrated circuit (IC) from other IC's on a semiconductor wafer | Warren M. Farnworth, William K. Waller, Leland R. Nevill, Raymond J. Beffa | 2001-11-06 |