Issued Patents All Time
Showing 51–72 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10770398 | Graphics processing unit and high bandwidth memory integration using integrated interface and silicon interposer | Owen R. Fay | 2020-09-08 |
| 10714456 | Dual sided fan-out package having low warpage across all temperatures | Mark E. Tuttle | 2020-07-14 |
| 10615154 | Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods | Todd O. Bolken | 2020-04-07 |
| 10593568 | Thrumold post package with reverse build up hybrid additive structure | John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle | 2020-03-17 |
| 10586780 | Semiconductor device modules including a die electrically connected to posts and related methods | Ashok Pachamuthu, Szu-Ying Ho, John F. Kaeding | 2020-03-10 |
| 10396003 | Stress tuned stiffeners for micro electronics package warpage control | Mark E. Tuttle | 2019-08-27 |
| 10366934 | Face down dual sided chip scale memory package | Akshay N. Singh, Yi Xu, Liana Foster, Steven Eskildsen | 2019-07-30 |
| 10325874 | Device module having a plurality of dies electrically connected by posts | Ashok Pachamuthu, Szu-Ying Ho, John F. Kaeding | 2019-06-18 |
| 10304805 | Dual sided fan-out package having low warpage across all temperatures | Mark E. Tuttle | 2019-05-28 |
| 10276487 | Semiconductor device with flexible circuit for enabling non-destructive attaching and detaching of device to system board | Eiichi Nakano | 2019-04-30 |
| 10192843 | Methods of making semiconductor device modules with increased yield | Ashok Pachamuthu, Szu-Ying Ho, John F. Kaeding | 2019-01-29 |
| 10153221 | Face down dual sided chip scale memory package | Akshay N. Singh, Yi Xu, Liana Foster, Steven Eskildsen | 2018-12-11 |
| 10103038 | Thrumold post package with reverse build up hybrid additive structure | John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle | 2018-10-16 |
| 9978730 | Method of assembly semiconductor device with through-package interconnect | Todd O. Bolken | 2018-05-22 |
| 9508686 | Semiconductor device assembly with package interconnect extending into overlying spacer material, and associated systems, devices, and methods | Todd O. Bolken | 2016-11-29 |
| 8906743 | Semiconductor device with molded casing and package interconnect extending therethrough, and associated systems, devices, and methods | Todd O. Bolken | 2014-12-09 |
| 6973236 | Vertical taper waveguide | Daniel W. So | 2005-12-06 |
| 6934455 | Waveguides with optical monitoring | Michael P. Skinner, Bidhan Chaudhuri, Mahmood Toofan, Gabel Chong, Achintya Bhowmik | 2005-08-23 |
| 5574770 | Method for controlling overload of main processor of distributed switching system with hierarchy structure | Byung Sun Lee, Young Sun Kim | 1996-11-12 |
| 5513255 | Method for controlling overload of distributed processors of full electronic switching system | Byung Sun Lee, Young-Su Kim | 1996-04-30 |
| 5513257 | Method for controlling overload in centralized and distributed operating hybrid switching system | Byung Sun Lee, Young Sun Kim | 1996-04-30 |
| 5241579 | Status management method of a signalling service device in an electric switching system | Dae Seoung KIM, Byung Ho Yae, Hyoung Joon Park | 1993-08-31 |