Issued Patents All Time
Showing 201–225 of 354 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7868454 | High performance sub-system design and assembly | — | 2011-01-11 |
| 7863654 | Top layers of metal for high performance IC's | — | 2011-01-04 |
| 7863739 | Low fabrication cost, fine pitch and high reliability solder bump | Jin-Yuan Lee, Ching-Cheng Huang | 2011-01-04 |
| 7592205 | Over-passivation process of forming polymer layer over IC chip | Ying-Chih Chen, Chiu-Ming Chou | 2009-09-22 |
| RE40887 | Semiconductor chip with redistribution metal layer | Tah-Kang Joseph Ting | 2009-09-01 |
| 7582966 | Semiconductor chip and method for fabricating the same | Chiu-Ming Chou | 2009-09-01 |
| 7582556 | Circuitry component and method for forming the same | Chien-Kang Chou, Ke-Hung Chen | 2009-09-01 |
| 7569422 | Chip package and method for fabricating the same | — | 2009-08-04 |
| 7554208 | Wirebond pad for semiconductor chip or wafer | Mark Chou, Michael Chen, Chien-Kang Chou | 2009-06-30 |
| 7547969 | Semiconductor chip with passivation layer comprising metal interconnect and contact pads | Chiu-Ming Chou, Chien-Kang Chou, Ching-San Lin | 2009-06-16 |
| 7534718 | Post passivation interconnection schemes on top of IC chips | Jin-Yuan Lee | 2009-05-19 |
| 7535102 | High performance sub-system design and assembly | — | 2009-05-19 |
| 7531417 | High performance system-on-chip passive device using post passivation process | — | 2009-05-12 |
| 7524759 | Post passivation interconnection schemes on top of IC chip | Jin-Yuan Lee | 2009-04-28 |
| 7521805 | Post passivation interconnection schemes on top of the IC chips | Chiu-Ming Chou, Chien-Kang Chou | 2009-04-21 |
| 7521812 | Method of wire bonding over active area of a semiconductor circuit | Jin-Yuan Lee, Ying-Chih Chen | 2009-04-21 |
| 7517778 | Structure of high performance combo chip and processing method | Jin-Yuan Lee | 2009-04-14 |
| 7511376 | Circuitry component with metal layer over die and extending to place not over die | Jin-Yuan Lee, Ching-Cheng Huang | 2009-03-31 |
| 7508059 | Stacked chip package with redistribution lines | Shih-Hsiung Lin, Hsin-Jung Lo, Ying-Chih Chen, Chiu-Ming Chou | 2009-03-24 |
| 7498255 | Post passivation interconnection schemes on top of the IC chips | — | 2009-03-03 |
| 7498196 | Structure and manufacturing method of chip scale package | Jin-Yuan Lee, Ching-Cheng Huang | 2009-03-03 |
| 7495304 | Chip package | Shih-Hsiung Lin, Hsin-Jung Lo | 2009-02-24 |
| 7482693 | Top layers of metal for high performance IC's | — | 2009-01-27 |
| 7482268 | Top layers of metal for integrated circuits | Chiu-Ming Chou, Chien-Kang Chou | 2009-01-27 |
| 7482259 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2009-01-27 |