Issued Patents All Time
Showing 1–25 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11721390 | DRAM with inter-section, page-data-copy scheme for low power and wide data access | Gyh-Bin Wang, Ming-Hung Wang | 2023-08-08 |
| 11250904 | DRAM with inter-section, page-data-copy scheme for low power and wide data access | Gyh-Bin Wang, Ming-Hung Wang | 2022-02-15 |
| 11183231 | Apparatus for enhancing prefetch access in memory module | Gyh-Bin Wang, Ming-Hung Wang | 2021-11-23 |
| 9997224 | Memory architecture with multi-bank memory cell array accessed by local drive circuit within memory bank | Ming-Hung Wang, Gyh-Bin Wang | 2018-06-12 |
| 9679622 | Method for controlling memory device asynchronously with respect to system clock, and related memory device and memory system | Gyh-Bin Wang, Yung-Ching Hsieh | 2017-06-13 |
| 9653148 | Multi-bank memory device and system | Gyh-Bin Wang, Ming-Hung Wang | 2017-05-16 |
| 9466355 | Memory architecture dividing memory cell array into independent memory banks | Gyh-Bin Wang | 2016-10-11 |
| 8754656 | High speed test circuit and method | Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Li-Chin Tien | 2014-06-17 |
| 8520427 | Memory cell and memory array utilizing the memory cell | — | 2013-08-27 |
| 7898319 | Efficiency improvement in charge pump system for low power application | Jenshou Hsu | 2011-03-01 |
| RE40887 | Semiconductor chip with redistribution metal layer | Mou-Shiung Lin | 2009-09-01 |
| 7475305 | Method of high speed data rate testing | Shih-Hsing Wang, Hong Jie Chen | 2009-01-06 |
| 7292494 | Internal power management scheme for a memory chip in deep power down mode | Jen-Shou Hsu, Ming-Hung Wang, Bor-Doou Rong | 2007-11-06 |
| 7031219 | Internal power management scheme for a memory chip in deep power down mode | Jen-Shoe Hsu, Ming-Hung Wang, Bor-Doou Rong | 2006-04-18 |
| 6943044 | Method of high speed data rate testing | Shih-Hsing Wang, Hong Jie Chen | 2005-09-13 |
| 6943783 | LCD controller which supports a no-scaling image without a frame buffer | Yin-Shing Lieu, Gyh-Bin Wang, Ming-Song Hwang | 2005-09-13 |
| 6894917 | DRAM refresh scheme with flexible frequency for active and standby mode | Chun Shiah, Shi-Huei Liu | 2005-05-17 |
| 6791382 | Noise reduction method and system for a multiple clock, mixed signal integrated circuit | Gyh-Bin Wang, Ming-Song Huang | 2004-09-14 |
| 6643166 | Low power SRAM redundancy repair scheme | Bor-Doou Rong, Shi-Huei Liu | 2003-11-04 |
| 6593649 | Methods of IC rerouting option for multiple package system applications | Mou-Shiung Lin | 2003-07-15 |
| 6515929 | Partial refresh feature in pseudo SRAM | Steven Li | 2003-02-04 |
| 6429710 | Input buffer with compensation for process variation | Gyh-Bin Wang, Chien-Te Wu | 2002-08-06 |
| 6237115 | Design for testability in very high speed memory | Bor-Doou Rong | 2001-05-22 |
| 6229726 | Integrated circuit chip having multiple package options | Gyh-Bin Wang, Chih-Tung Wang | 2001-05-08 |
| 6198340 | High efficiency CMOS pump circuit | Gyh-Bin Wang, Ming-Hung Wang | 2001-03-06 |