Issued Patents All Time
Showing 25 most recent of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12361998 | Sustainable DRAM having principle power supply voltage unified with logic circuit | Chao-Chun Lu, Bor-Doou Rong | 2025-07-15 |
| 12354646 | Dynamic memory with sustainable storage architecture | Chao-Chun Lu, Bor-Doou Rong | 2025-07-08 |
| 12068020 | Dynamic memory with sustainable storage architecture and clean up circuit | Chao-Chun Lu, Bor-Doou Rong | 2024-08-20 |
| 11798613 | Dynamic memory with long retention time | Chao-Chun Lu, Bor-Doou Rong | 2023-10-24 |
| 11789893 | Memory system, memory controller and memory chip | — | 2023-10-17 |
| 11646066 | Memory controller and related memory | — | 2023-05-09 |
| 11302383 | Dynamic memory with sustainable storage architecture | Chao-Chun Lu, Bor-Doou Rong | 2022-04-12 |
| 10387047 | Memory circuit with improved read and write access | Cheng-Nan Chang, Yu-Hui Sung | 2019-08-20 |
| 10255965 | Memory circuit capable of being quickly written in data | Yu-Hui Sung | 2019-04-09 |
| 10037787 | Circuit for outputting information of a memory circuit during a self-refresh mode and related method thereof | Ho-Yin Chen, Cheng-Nan Chang | 2018-07-31 |
| 9773533 | Memory with low current consumption and method for reducing current consumption of a memory | — | 2017-09-26 |
| 9589931 | Bundled memory and manufacture method for a bundled memory with an external input/output bus | Bor-Doou Rong | 2017-03-07 |
| 9465430 | Memory with variable operation voltage and the adjusting method thereof | Bor-Doou Rong | 2016-10-11 |
| 9214448 | Bundled memory and manufacture method for a bundled memory with an external input/output bus | Bor-Doou Rong | 2015-12-15 |
| 9070558 | Bundled memory and manufacture method for a bundled memory with an external input/output bus | Bor-Doou Rong | 2015-06-30 |
| 9065444 | Power-up initial circuit | Yen-An Chang, Hao-Jan Yang | 2015-06-23 |
| 8872540 | Method of sharing in use an impedance matching circuit of a memory circuit to perform an initial calibration and a full time refresh mode calibration, and memory circuit with an impedance matching circuit capable of being used in an initial calibration and a full time refresh mode calibration | Sen-Fu Hong, Wen-Wey Chen | 2014-10-28 |
| 8854911 | Memory and method of refreshing a memory | Sen-Fu Hong | 2014-10-07 |
| 8824238 | Memory device with bi-directional tracking of timing constraints | Ho-Yin Chen, Hung-Jen Chang | 2014-09-02 |
| 8823446 | Current mirror with immunity for the variation of threshold voltage and the generation method thereof | Hao-Jan Yang, Ho-Yin Chen, Kuo-Chen Lai | 2014-09-02 |
| 8755236 | Latch system applied to a plurality of banks of a memory circuit | Shi-Huei Liu, Cheng-Nan Chang | 2014-06-17 |
| 8723570 | Delay-locked loop and method for a delay-locked loop generating an application clock | Feng-Chia Chang, Yu-Chou Ke, Chi-Wei Yen | 2014-05-13 |
| 8653855 | Input buffer system with a dual-input buffer switching function and method thereof | Sen-Fu Hong, Chia-Ming Chen | 2014-02-18 |
| 8536903 | Output stage circuit for outputting a driving current varying with a process | Hao-Jan Yang, Ching-Ying Hsu | 2013-09-17 |
| 8432206 | Delay lock loop system with a self-tracking function and method thereof | Der-Min Yuan, Kuang-Fu Teng, Feng-Chia Chang | 2013-04-30 |