Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8384454 | DLL circuit with dynamic phase-chasing function and method thereof | Yu-Sheng Lai, Feng-Chia Chang | 2013-02-26 |
| 8223566 | Memory device and memory control method | Shi-Huei Liu | 2012-07-17 |
| 8144526 | Method to improve the write speed for memory products | — | 2012-03-27 |
| 7983102 | Data detecting apparatus and methods thereof | Shih-Hsing Wang, Der-Min Yuan, Bor-Doou Rong | 2011-07-19 |
| 7969253 | VCO with stabilized reference current source module | Cheng-Nan Chang, Yu-Sheng Lai | 2011-06-28 |
| 7940093 | Output circuit with overshoot-reducing function | Chi-Fa Lien, Sen-Fu Hong | 2011-05-10 |
| 7928767 | Buffer-driving circuit capable of increasing responding speed and prolonging lifespan, buffer, and method thereof | Tzu-Jen Ting, Yu-Hui Sung | 2011-04-19 |
| 7915922 | Buffer-driving circuit capable of increasing responding speed and prolonging lifespan, buffer, and method thereof | Tzu-Jen Ting, Yu-Hui Sung | 2011-03-29 |
| 7880517 | Delayed-locked loop with power-saving function | Chun-Peng Wu, Hsien-Sheng Huang | 2011-02-01 |
| 7843222 | Buffer-driving circuit capable of increasing responding speed and prolonging lifespan, buffer, and method thereof | Tzu-Jen Ting, Yu-Hui Sung | 2010-11-30 |
| 7755406 | Duty cycle correction circuit with wide-frequency working range | Hsien-Sheng Huang | 2010-07-13 |
| 7738306 | Method to improve the write speed for memory products | — | 2010-06-15 |
| 7609579 | Memory module with failed memory cell repair function and method thereof | Tzu-Jen Ting, Ho-Yin Chen | 2009-10-27 |
| 7514951 | Negative voltage noise-free circuit for multi-functional pad | — | 2009-04-07 |
| 7515669 | Dynamic input setup/hold time improvement architecture | Bor-Doou Rong, Shi-Huei Liu | 2009-04-07 |
| 7508726 | Signal sensing circuit and semiconductor memory device using the same | Chun-Peng Wu, Cheng-Nan Chang | 2009-03-24 |
| 7466013 | Semiconductor die structure featuring a triple pad organization | — | 2008-12-16 |
| 7414448 | Duty cycle correction circuit | Hsien-Sheng Huang | 2008-08-19 |
| 7362144 | Low jitter input buffer with small input signal swing | — | 2008-04-22 |
| 7054178 | Datapath architecture for high area efficiency | Ming-Hung Wang, Chun-Chi Shen | 2006-05-30 |
| 6894917 | DRAM refresh scheme with flexible frequency for active and standby mode | Tah-Kang Joseph Ting, Shi-Huei Liu | 2005-05-17 |
| 6861877 | Circuit to independently adjust rise and fall edge timing of a signal | — | 2005-03-01 |
| 6130853 | Address decoding scheme for DDR memory | Ming-Hung Wang, Gyh-Bin Wang | 2000-10-10 |
| 6101138 | Area efficient global row redundancy scheme for DRAM | Bor-Doou Rong, Jeng-Tzong Shih, Po-Hung Chen | 2000-08-08 |
| 5815463 | Flexible time write operation | Jeng-Tzong Shih, Tah-Kang Joseph Ting | 1998-09-29 |