Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7919989 | Circuit architecture for effective compensating the time skew of circuit | — | 2011-04-05 |
| 7796463 | Self-feedback control pipeline architecture for memory read path applications | Ming-Hung Wang | 2010-09-14 |
| 7525368 | Fuse circuit | — | 2009-04-28 |
| 7391656 | Self-feedback control pipeline architecture for memory read path applications | Ming-Hung Wang | 2008-06-24 |
| 7098722 | Low power design for fuse control circuit | Bor-Doou Rong | 2006-08-29 |
| 6661719 | Wafer level burn-in for memory integrated circuit | Shi-Huei Liu, Bor-Doou Rong | 2003-12-09 |
| 6643732 | Delayed read/write scheme for SRAM interface compatible DRAM | — | 2003-11-04 |
| 6529046 | Minimum pulse width detection and regeneration circuit | — | 2003-03-04 |
| 6366123 | Input buffer circuit for low power application | Shi-Huei Liu | 2002-04-02 |
| 6323712 | Delay circuit with voltage compensation | — | 2001-11-27 |
| 6101138 | Area efficient global row redundancy scheme for DRAM | Chun Shiah, Bor-Doou Rong, Po-Hung Chen | 2000-08-08 |
| 5815463 | Flexible time write operation | Chun Shiah, Tah-Kang Joseph Ting | 1998-09-29 |
| 5767718 | High speed conditional synchronous one shot circuit | — | 1998-06-16 |
| 5708688 | High speed programmable burst address generation circuit | Tah-Kang Joseph Ting, Ghy-Bin Wang | 1998-01-13 |
| 5689200 | High speed glitch-free transition detection circuit with disable control | Tah-Kang Joseph Ting, Yung-Ching Hsieh | 1997-11-18 |