Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426183 | Adjustable and changeable modular control panel | Wei Teng | 2025-09-23 |
| 12002637 | Keyboard and key structure capable of displaying instant image | Chia-Hsin Tsai | 2024-06-04 |
| 11755685 | Apparatus for data processing in conjunction with memory array access | Gyh-Bin Wang, Cheng-En Shieh | 2023-09-12 |
| 11721390 | DRAM with inter-section, page-data-copy scheme for low power and wide data access | Gyh-Bin Wang, Tah-Kang Joseph Ting | 2023-08-08 |
| 11520934 | Method for preventing differential cryptanalysis attack | Zhikuang Cai, Xun Xu, Zixuan Wang, Henglu Wang, Jingqi Yao +2 more | 2022-12-06 |
| 11437087 | Method and apparatus for accumulating and storing respective access counts of word lines in memory module | Chun-Peng Wu | 2022-09-06 |
| 11250904 | DRAM with inter-section, page-data-copy scheme for low power and wide data access | Gyh-Bin Wang, Tah-Kang Joseph Ting | 2022-02-15 |
| 11183231 | Apparatus for enhancing prefetch access in memory module | Gyh-Bin Wang, Tah-Kang Joseph Ting | 2021-11-23 |
| 9997224 | Memory architecture with multi-bank memory cell array accessed by local drive circuit within memory bank | Gyh-Bin Wang, Tah-Kang Joseph Ting | 2018-06-12 |
| 9653148 | Multi-bank memory device and system | Tah-Kang Joseph Ting, Gyh-Bin Wang | 2017-05-16 |
| 8754656 | High speed test circuit and method | Tah-Kang Joseph Ting, Gyh-Bin Wang, Chun-Peng Wu, Li-Chin Tien | 2014-06-17 |
| 7796463 | Self-feedback control pipeline architecture for memory read path applications | Jeng-Tzong Shih | 2010-09-14 |
| 7676708 | Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application | — | 2010-03-09 |
| 7634698 | Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application | — | 2009-12-15 |
| 7613962 | Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application | — | 2009-11-03 |
| 7551018 | Decoupling capacitor circuit | Jen-Shou Hsu | 2009-06-23 |
| 7482884 | Ring oscillator with a two-stage phase blender for generating multi-phase clock signals | Peng Lin, Ming-Chi Lin | 2009-01-27 |
| 7404116 | Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application | — | 2008-07-22 |
| 7391656 | Self-feedback control pipeline architecture for memory read path applications | Jeng-Tzong Shih | 2008-06-24 |
| 7292083 | Comparator circuit with Schmitt trigger hysteresis character | Yen-An Chang | 2007-11-06 |
| 7292494 | Internal power management scheme for a memory chip in deep power down mode | Jen-Shou Hsu, Tah-Kang Joseph Ting, Bor-Doou Rong | 2007-11-06 |
| 7054178 | Datapath architecture for high area efficiency | Chun Shiah, Chun-Chi Shen | 2006-05-30 |
| 7031219 | Internal power management scheme for a memory chip in deep power down mode | Jen-Shoe Hsu, Tah-Kang Joseph Ting, Bor-Doou Rong | 2006-04-18 |
| 6922192 | Wide-range and balanced display position adjustment method for LCD controller | — | 2005-07-26 |
| 6856358 | Phase-increase induced backporch decrease (PIBD) phase recovery method for video signal processing | — | 2005-02-15 |