Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12361998 | Sustainable DRAM having principle power supply voltage unified with logic circuit | Chao-Chun Lu, Chun Shiah | 2025-07-15 |
| 12354646 | Dynamic memory with sustainable storage architecture | Chao-Chun Lu, Chun Shiah | 2025-07-08 |
| 12068020 | Dynamic memory with sustainable storage architecture and clean up circuit | Chao-Chun Lu, Chun Shiah | 2024-08-20 |
| 11798613 | Dynamic memory with long retention time | Chao-Chun Lu, Chun Shiah | 2023-10-24 |
| 11302383 | Dynamic memory with sustainable storage architecture | Chao-Chun Lu, Chun Shiah | 2022-04-12 |
| 9601456 | System-in-package module and manufacture method for a system-in-package module | Weng-Dah Ken | 2017-03-21 |
| 9589931 | Bundled memory and manufacture method for a bundled memory with an external input/output bus | Chun Shiah | 2017-03-07 |
| 9465430 | Memory with variable operation voltage and the adjusting method thereof | Chun Shiah | 2016-10-11 |
| 9214448 | Bundled memory and manufacture method for a bundled memory with an external input/output bus | Chun Shiah | 2015-12-15 |
| 9070558 | Bundled memory and manufacture method for a bundled memory with an external input/output bus | Chun Shiah | 2015-06-30 |
| 7983102 | Data detecting apparatus and methods thereof | Shih-Hsing Wang, Der-Min Yuan, Chun Shiah | 2011-07-19 |
| 7515669 | Dynamic input setup/hold time improvement architecture | Chun Shiah, Shi-Huei Liu | 2009-04-07 |
| 7478294 | Time controllable sensing scheme for sense amplifier in memory IC test | Shi-Huei Liu | 2009-01-13 |
| 7434985 | Calibrated built-in temperature sensor and calibration method thereof | Jen-Shou Hsu | 2008-10-14 |
| 7292494 | Internal power management scheme for a memory chip in deep power down mode | Jen-Shou Hsu, Tah-Kang Joseph Ting, Ming-Hung Wang | 2007-11-06 |
| 7098722 | Low power design for fuse control circuit | Jeng-Tzong Shih | 2006-08-29 |
| 7031219 | Internal power management scheme for a memory chip in deep power down mode | Jen-Shoe Hsu, Tah-Kang Joseph Ting, Ming-Hung Wang | 2006-04-18 |
| 6934899 | Variable self-time scheme for write recovery by low speed tester | Der-Min Yuan | 2005-08-23 |
| 6661719 | Wafer level burn-in for memory integrated circuit | Jeng-Tzong Shih, Shi-Huei Liu | 2003-12-09 |
| 6643166 | Low power SRAM redundancy repair scheme | Tah-Kang Joseph Ting, Shi-Huei Liu | 2003-11-04 |
| 6377492 | Memory architecture for read and write at the same time using a conventional cell | Ghy-Bin Wang | 2002-04-23 |
| 6237115 | Design for testability in very high speed memory | Tah-Kang Joseph Ting | 2001-05-22 |
| 6101138 | Area efficient global row redundancy scheme for DRAM | Chun Shiah, Jeng-Tzong Shih, Po-Hung Chen | 2000-08-08 |
| 6058069 | Protection circuit to ensure DRAM signal in write cycle | Tah-Kang Joseph Ting, Tien-Hsin Chang | 2000-05-02 |
| 5737271 | Semiconductor memory arrays | Tah-Kang Joseph Ting, Yung-Ching Hsieh | 1998-04-07 |