Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10778204 | Comparator circuit with low power consumption and low kickback noise | Chung-Chih Hung | 2020-09-15 |
| 10439621 | Two-step switching method for a circuit switch | Chung-Chih Hung | 2019-10-08 |
| 10277122 | Charge pump circuit and phase locked loop system using the same | Chung-Chih Hung | 2019-04-30 |
| 9093179 | Chip capable of improving test coverage of pads and related method thereof | Ming-Cheng Liang, Kuo-Cheng Ting | 2015-07-28 |
| 8773931 | Method of detecting connection defects of memory and memory capable of detecting connection defects thereof | Min-Chih Chang, Te-Yi Yu, Lien-Sheng Yang | 2014-07-08 |
| 8773179 | Input receiver and operation method thereof | Yi-Hao Chang, Wen-Tung Yang, Yen-An Chang | 2014-07-08 |
| 8520453 | Device for generating a test pattern of a memory chip and method thereof | Chun-Ching Hsia, Che-Chun Ou Yang | 2013-08-27 |
| 8345500 | Memory having a disabling circuit and method for disabling the memory | Der-Min Yuan | 2013-01-01 |
| 8201035 | Testing system and method thereof | Kuo-Hua Lee, Chih-Ming Cheng | 2012-06-12 |
| 8125838 | System in package integrated circuit with self-generating reference voltage | Der-Min Yuan | 2012-02-28 |
| 7983102 | Data detecting apparatus and methods thereof | Der-Min Yuan, Bor-Doou Rong, Chun Shiah | 2011-07-19 |
| 7978525 | Data flow scheme for low power DRAM | Der-Min Yuan | 2011-07-12 |
| 7924641 | Data flow scheme for low power DRAM | Der-Min Yuan | 2011-04-12 |
| 7663949 | Memory row architecture having memory row redundancy repair function | Der-Min Yuan | 2010-02-16 |
| 7475305 | Method of high speed data rate testing | Tah-Kang Joseph Ting, Hong Jie Chen | 2009-01-06 |
| 7359265 | Data flow scheme for low power DRAM | Der-Min Yuan | 2008-04-15 |
| 6943044 | Method of high speed data rate testing | Tah-Kang Joseph Ting, Hong Jie Chen | 2005-09-13 |