| 11755685 |
Apparatus for data processing in conjunction with memory array access |
Ming-Hung Wang, Cheng-En Shieh |
2023-09-12 |
| 11721390 |
DRAM with inter-section, page-data-copy scheme for low power and wide data access |
Tah-Kang Joseph Ting, Ming-Hung Wang |
2023-08-08 |
| 11250904 |
DRAM with inter-section, page-data-copy scheme for low power and wide data access |
Tah-Kang Joseph Ting, Ming-Hung Wang |
2022-02-15 |
| 11183231 |
Apparatus for enhancing prefetch access in memory module |
Ming-Hung Wang, Tah-Kang Joseph Ting |
2021-11-23 |
| 10978377 |
Semiconductor chip set with double-sided off-chip bonding structure |
— |
2021-04-13 |
| 10559374 |
Circuit topology of memory chips with embedded function test pattern generation module connected to normal access port physical layer |
Chun-Kai Wang |
2020-02-11 |
| 9997224 |
Memory architecture with multi-bank memory cell array accessed by local drive circuit within memory bank |
Ming-Hung Wang, Tah-Kang Joseph Ting |
2018-06-12 |
| 9679622 |
Method for controlling memory device asynchronously with respect to system clock, and related memory device and memory system |
Tah-Kang Joseph Ting, Yung-Ching Hsieh |
2017-06-13 |
| 9653148 |
Multi-bank memory device and system |
Tah-Kang Joseph Ting, Ming-Hung Wang |
2017-05-16 |
| 9466355 |
Memory architecture dividing memory cell array into independent memory banks |
Tah-Kang Joseph Ting |
2016-10-11 |
| 8754656 |
High speed test circuit and method |
Tah-Kang Joseph Ting, Ming-Hung Wang, Chun-Peng Wu, Li-Chin Tien |
2014-06-17 |
| 7961966 |
Digitized image stabilization using energy analysis method |
Wen Lu |
2011-06-14 |
| 7860202 |
Method and circuit for transferring data stream across multiple clock domains |
Hsien-Sheng Huang |
2010-12-28 |
| 6943783 |
LCD controller which supports a no-scaling image without a frame buffer |
Tah-Kang Joseph Ting, Yin-Shing Lieu, Ming-Song Hwang |
2005-09-13 |
| 6791382 |
Noise reduction method and system for a multiple clock, mixed signal integrated circuit |
Tah-Kang Joseph Ting, Ming-Song Huang |
2004-09-14 |
| 6543015 |
Efficient data compression circuit for memory testing |
Der-Min Yuan |
2003-04-01 |
| 6453381 |
DDR DRAM data coherence scheme |
Der-Min Yuan |
2002-09-17 |
| 6429710 |
Input buffer with compensation for process variation |
Tah-Kang Joseph Ting, Chien-Te Wu |
2002-08-06 |
| 6229726 |
Integrated circuit chip having multiple package options |
Chih-Tung Wang, Tah-Kang Joseph Ting |
2001-05-08 |
| 6198340 |
High efficiency CMOS pump circuit |
Tah-Kang Joseph Ting, Ming-Hung Wang |
2001-03-06 |
| 6130853 |
Address decoding scheme for DDR memory |
Ming-Hung Wang, Chun Shiah |
2000-10-10 |
| 6064613 |
Pre-sense amplifier with reduced output swing |
— |
2000-05-16 |
| 5999032 |
Multiple phase synchronous race delay clock distribution circuit with skew compensation |
Li-Chin Tien |
1999-12-07 |
| 5923613 |
Latched type clock synchronizer with additional 180.degree.-phase shift clock |
Li-Chin Tien |
1999-07-13 |