Issued Patents All Time
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6058069 | Protection circuit to ensure DRAM signal in write cycle | Tien-Hsin Chang, Bor-Doou Rong | 2000-05-02 |
| 5815463 | Flexible time write operation | Jeng-Tzong Shih, Chun Shiah | 1998-09-29 |
| 5801997 | Ping-pong boost circuit | Chung-Wei Hsieh, Yung-Ching Hsieh | 1998-09-01 |
| 5754479 | Distributed bit switch logically interleaved for block write performance | Yung-Ching Hsieh, Chun Shiah | 1998-05-19 |
| 5737271 | Semiconductor memory arrays | Bor-Doou Rong, Yung-Ching Hsieh | 1998-04-07 |
| 5723994 | Level boost restoration circuit | Chun Shiah, Bor-Doou Rong | 1998-03-03 |
| 5708688 | High speed programmable burst address generation circuit | Ghy-Bin Wang, Jeng-Tzong Shih | 1998-01-13 |
| 5703832 | t.sub.RAS protection circuit | Ching-Chih Hsieh, Bor-Doou Rong | 1997-12-30 |
| 5689200 | High speed glitch-free transition detection circuit with disable control | Jeng-Tzong Shih, Yung-Ching Hsieh | 1997-11-18 |
| 5671189 | Low standby power redundancy circuit | Bor-Doou Rong, Jun Luo | 1997-09-23 |
| 5646551 | Mixed mode output buffer circuit for CMOSIC | — | 1997-07-08 |
| 5633604 | Mixed mode output buffer circuit for CMOSIC | — | 1997-05-27 |
| 5604457 | Mixed mode output buffer circuit for CMOSIC | — | 1997-02-18 |
| 5568430 | Self timed address locking and data latching circuit | — | 1996-10-22 |
| 5563831 | Timing reference circuit for bitline precharge in memory arrays | — | 1996-10-08 |
| 5534789 | Mixed mode output buffer circuit for CMOSIC | — | 1996-07-09 |
| 5530395 | Supply voltage level control using reference voltage generator and comparator circuits | — | 1996-06-25 |
| 5036378 | Memory device | Chih-Yuan Lu | 1991-07-30 |
| 4931670 | TTL and CMOS logic compatible GAAS logic family | — | 1990-06-05 |