Issued Patents All Time
Showing 176–200 of 354 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7960842 | Structure of high performance combo chip and processing method | Jin-Yuan Lee | 2011-06-14 |
| 7960269 | Method for forming a double embossing structure | Hsin-Jung Lo, Chiu-Ming Chou, Chien-Kang Chou | 2011-06-14 |
| 7960212 | Structure of high performance combo chip and processing method | Jin-Yuan Lee | 2011-06-14 |
| 7947978 | Semiconductor chip with bond area | Huei-Mei Yen, Chiu-Ming Chou, Hsin-Jung Lo, Ke-Hung Chen | 2011-05-24 |
| 7932603 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2011-04-26 |
| 7932172 | Semiconductor chip and process for forming the same | Chien-Kang Chou, Hsin-Jung Lo | 2011-04-26 |
| 7928576 | Post passivation interconnection schemes on top of the IC chips | — | 2011-04-19 |
| 7923366 | Post passivation interconnection schemes on top of IC chip | Jin-Yuan Lee | 2011-04-12 |
| 7923848 | High performance sub-system design and assembly | — | 2011-04-12 |
| 7919873 | Structure of high performance combo chip and processing method | Jin-Yuan Lee | 2011-04-05 |
| 7919867 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2011-04-05 |
| 7919865 | Post passivation interconnection schemes on top of IC chip | Jin-Yuan Lee | 2011-04-05 |
| 7919412 | Over-passivation process of forming polymer layer over IC chip | Ying-Chih Chen, Chiu-Ming Chou | 2011-04-05 |
| 7915161 | Post passivation interconnection schemes on top of IC chip | Jin-Yuan Lee | 2011-03-29 |
| 7915734 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2011-03-29 |
| 7915157 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2011-03-29 |
| 7906849 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2011-03-15 |
| 7906422 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2011-03-15 |
| 7902679 | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump | Ming-Ta Lei, Chuen-Jye Lin | 2011-03-08 |
| 7902067 | Post passivation interconnection schemes on top of the IC chips | Jin-Yuan Lee | 2011-03-08 |
| 7898058 | Integrated chip package structure using organic substrate and method of manufacturing the same | Jin-Yuan Lee, Ching-Cheng Huang | 2011-03-01 |
| 7892965 | Post passivation interconnection schemes on top of IC chip | Jin-Yuan Lee | 2011-02-22 |
| 7884479 | Top layers of metal for high performance IC's | — | 2011-02-08 |
| 7880304 | Post passivation interconnection schemes on top of the IC chips | Chiu-Ming Chou, Chien-Kang Chou | 2011-02-01 |
| 7868463 | High performance sub-system design and assembly | — | 2011-01-11 |