Issued Patents All Time
Showing 226–250 of 354 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7479450 | Post passivation interconnection schemes on top of the IC chips | Jin-Yuan Lee | 2009-01-20 |
| 7473999 | Semiconductor chip and process for forming the same | Chien-Kang Chou, Hsin-Jung Lo | 2009-01-06 |
| 7470997 | Wirebond pad for semiconductor chip or wafer | Michael Chen, Chien-Kang Chou, Mark Chou | 2008-12-30 |
| 7470988 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2008-12-30 |
| 7470927 | Semiconductor chip with coil element over passivation layer | Wen-Chieh Lee, Chien-Kang Chou, Yi-Cheng Liu, Chiu-Ming Chou, Jin-Yuan Lee | 2008-12-30 |
| 7468551 | Multiple chips bonded to packaging structure with low noise and multiple selectable functions | Bryan Peng | 2008-12-23 |
| 7468545 | Post passivation structure for a semiconductor device and packaging process for same | Chien-Kang Chou, Ke-Hung Chen | 2008-12-23 |
| 7468316 | Low fabrication cost, fine pitch and high reliability solder bump | Jin-Yuan Lee, Ching-Cheng Huang | 2008-12-23 |
| 7466007 | Post passivation interconnection schemes on top of IC chip | Jin-Yuan Lee | 2008-12-16 |
| 7465975 | Top layers of metal for high performance IC's | — | 2008-12-16 |
| 7465654 | Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures | Chiu-Ming Chou | 2008-12-16 |
| 7465653 | Reliable metal bumps on top of I/O pads after removal of test probe marks | Ching-Cheng Huang, Chuen-Jye Lin, Ming-Ta Lei | 2008-12-16 |
| 7462938 | Post passivation interconnection schemes on top of IC chip | Jin-Yuan Lee | 2008-12-09 |
| 7462558 | Method for fabricating a circuit component | Chiu-Ming Chou, Chien-Kang Chou, Hsin-Jung Lo | 2008-12-09 |
| 7459791 | Post passivation interconnection schemes on top of IC chip | Jin-Yuan Lee | 2008-12-02 |
| 7459790 | Post passivation interconnection schemes on top of the IC chips | — | 2008-12-02 |
| 7459761 | High performance system-on-chip using post passivation process | — | 2008-12-02 |
| 7456100 | Top layers of metal for high performance IC's | — | 2008-11-25 |
| 7452803 | Method for fabricating chip structure | Chiu-Ming Chou, Chien-Kang Chou, Hsin-Jung Lo | 2008-11-18 |
| 7449752 | Post passivation interconnection schemes on top of the IC chips | Jin-Yuan Lee | 2008-11-11 |
| 7446035 | Post passivation interconnection schemes on top of IC chips | Jin-Yuan Lee | 2008-11-04 |
| 7446031 | Post passivation interconnection schemes on top of IC chips | Jin-Yuan Lee | 2008-11-04 |
| 7443034 | Post passivation interconnection schemes on top of the IC chips | Jin-Yuan Lee | 2008-10-28 |
| 7443033 | Post passivation interconnection schemes on top of the IC chips | Jin-Yuan Lee | 2008-10-28 |
| 7442969 | Top layers of metal for high performance IC's | — | 2008-10-28 |