Issued Patents All Time
Showing 101–125 of 354 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8426958 | Stacked chip package with redistribution lines | Shih-Hsiung Lin, Hsin-Jung Lo, Ying-Chih Chen, Chiu-Ming Chou | 2013-04-23 |
| 8421227 | Semiconductor chip structure | Jin-Yuan Lee | 2013-04-16 |
| 8421222 | Chip package having a chip combined with a substrate via a copper pillar | Shih-Hsiung Lin | 2013-04-16 |
| 8421158 | Chip structure with a passive device and method for forming the same | — | 2013-04-16 |
| 8420520 | Non-cyanide gold electroplating for fine-line gold traces and gold pads | Jin-Yuan Lee | 2013-04-16 |
| 8415800 | Top layers of metal for high performance IC's | — | 2013-04-09 |
| 8399989 | Metal pad or metal bump over pad exposed by passivation layer | Hsin-Jung Lo, Chiu-Ming Chou, Chien-Kang Chou, Ke-Hung Chen | 2013-03-19 |
| 8399988 | High performance sub-system design and assembly | — | 2013-03-19 |
| 8384508 | Method for making high-performance RF integrated circuits | Jin-Yuan Lee | 2013-02-26 |
| 8373202 | Integrated circuit chips with fine-line metal and over-passivation metal | Jin-Yuan Lee, Chien-Kang Chou | 2013-02-12 |
| 8368213 | Low fabrication cost, fine pitch and high reliability solder bump | Jin-Yuan Lee, Ching-Cheng Huang | 2013-02-05 |
| 8368204 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2013-02-05 |
| 8368193 | Chip package | Shih-Hsiung Lin, Hsin-Jung Lo | 2013-02-05 |
| 8368150 | High performance IC chip having discrete decoupling capacitors attached to its IC surface | — | 2013-02-05 |
| 8362588 | Semiconductor chip with coil element over passivation layer | Wen-Chieh Lee, Chien-Kang Chou, Yi-Cheng Liu, Chiu-Ming Chou, Jin-Yuan Lee | 2013-01-29 |
| 8350386 | Top layers of metal for high performance IC's | Jin-Yuan Lee | 2013-01-08 |
| 8344524 | Wire bonding method for preventing polymer cracking | Chiu-Ming Chou, Shih-Hsiung Lin, Hsin-Jung Lo | 2013-01-01 |
| 8319354 | Semiconductor chip with post-passivation scheme formed over passivation layer | Hsin-Jung Lo, Chien-Kang Chou, Chiu-Ming Chou, Ching-San Lin | 2012-11-27 |
| 8304766 | Semiconductor chip with a bonding pad having contact and test areas | Huei-Mei Yen, Hsin-Jung Lo, Chiu-Ming Chou, Ke-Hung Chen | 2012-11-06 |
| 8304907 | Top layers of metal for integrated circuits | Chiu-Ming Chou, Chien-Kang Chou | 2012-11-06 |
| 8294279 | Chip package with dam bar restricting flow of underfill | Ke-Hung Chen, Shih-Hsiung Lin | 2012-10-23 |
| RE43674 | Post passivation metal scheme for high-performance integrated circuit devices | Jin-Yuan Lee, Ming-Ta Lei, Ching-Cheng Huang | 2012-09-18 |
| 8242601 | Semiconductor chip with passivation layer comprising metal interconnect and contact pads | Chiu-Ming Chou, Chien-Kang Chou, Ching-San Lin | 2012-08-14 |
| 8232192 | Process of bonding circuitry components | Shih-Hsiung Lin, Hsin-Jung Lo | 2012-07-31 |
| 8211791 | Method for fabricating circuitry component | Jin-Yuan Lee, Ching-Cheng Huang | 2012-07-03 |