Issued Patents All Time
Showing 51–75 of 143 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6703860 | I/O block for a programmable interconnect circuit | Jinghui Zhu | 2004-03-09 |
| 6661254 | Programmable interconnect circuit with a phase-locked loop | Jinghui Zhu, Kuang Chi, Chienkuang Chen | 2003-12-09 |
| 6653861 | Multi-level routing structure for a programmable interconnect circuit | Jinghui Zhu | 2003-11-25 |
| 6653860 | Enhanced macrocell module having expandable product term sharing capability for use in high density CPLD architectures | Xiaojie He, Claudia A. Stanley, Larry R. Metzger, Chong M. Lee | 2003-11-25 |
| 6650141 | High speed interface for a programmable interconnect circuit | Jinghui Zhu, Kuang Chi, Chienkuang Chen | 2003-11-18 |
| 6650142 | Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use | Fabiano Fontana, Gilles Bosco | 2003-11-18 |
| 6621298 | Variable grain architecture for FPGA integrated circuits | Herman M. Chang, Bradley A. Sharpe-Geisler, Giap H. Tran | 2003-09-16 |
| 6590415 | Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources | Bradley A. Sharpe-Geisler, Herman M. Chang, Bai Nguyen, Giap H. Tran | 2003-07-08 |
| 6567969 | Configurable logic array including lookup table means for generating functions of different numbers of input terms | Michael J. Wright, Ju Shen | 2003-05-20 |
| 6531890 | Programmable optimized-distribution logic allocator for a high-density complex PLD | Bradley A. Sharpe-Geisler, Nicholas A. Schmitz | 2003-03-11 |
| 6526558 | Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources | Bradley A. Sharpe-Geisler, Herman M. Chang, Bai Nguyen, Giap H. Tran | 2003-02-25 |
| 6380759 | Variable grain architecture for FPGA integrated circuits | Herman M. Chang, Bradley A. Sharpe-Geisler, Giap H. Tran | 2002-04-30 |
| 6348813 | Scalable architecture for high density CPLD's having two-level hierarchy of routing resources | Claudia A. Stanley, Xiaojie He, Larry R. Metzger, Robert A. Simon, Kerry A. Ilgenstein | 2002-02-19 |
| 6292930 | Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resources | Bradley A. Sharpe-Geisler, Herman M. Chang, Giap H. Tran | 2001-09-18 |
| 6275064 | Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits | Herman M. Chang, Bradley A. Sharpe-Geisler, Giap H. Tran | 2001-08-14 |
| 6249144 | Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources | Bradley A. Sharpe-Geisler, Herman M. Chang, Bai Nguyen, Giap H. Tran | 2001-06-19 |
| 6216257 | FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks | Herman M. Chang, Bradley A. Sharpe-Geisler, Giap H. Tran, Bai Nguyen | 2001-04-10 |
| 6211695 | FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections | Herman M. Chang, Bradley A. Sharpe-Geisler, Bai Nguyen | 2001-04-03 |
| 6204686 | Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources | Bradley A. Sharpe-Geisler, Herman M. Chang, Bai Nguyen, Giap H. Tran | 2001-03-20 |
| 6191612 | Enhanced I/O control flexibility for generating control signals | Bradley A. Sharpe-Geisler, Giap H. Tran | 2001-02-20 |
| 6184713 | Scalable architecture for high density CPLDS having two-level hierarchy of routing resources | Claudia A. Stanley, Xiaojie He, Larry R. Metzger, Robert A. Simon, Kerry A. Ilgenstein | 2001-02-06 |
| 6181163 | FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals | Herman M. Chang, Bradley A. Sharpe-Geisler, Bai Nguyen | 2001-01-30 |
| 6163168 | Efficient interconnect network for use in FPGA device having variable grain architecture | Bai Nguyen, Bradley A. Sharpe-Geisler, Jack T. Wong, Herman M. Chang | 2000-12-19 |
| 6154051 | Tileable and compact layout for super variable grain blocks within FPGA device | Bai Nguyen, Bradley A. Sharpe-Geisler, Jack T. Wong, Herman M. Chang, Giap H. Tran | 2000-11-28 |
| 6150841 | Enhanced macrocell module for high density CPLD architectures | Claudia A. Stanley, Xiaojie He, Chong M. Lee, Robert M. Balzli, Jr., Larry R. Metzger +1 more | 2000-11-21 |