Issued Patents All Time
Showing 101–125 of 143 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5612631 | An I/O macrocell for a programmable logic device | Jerry D. Moench | 1997-03-18 |
| 5598346 | Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of logic blocks | Michael J. Wright, Ju Shen | 1997-01-28 |
| 5594365 | Flexible block clock generation circuit for providing clock signals to clocked elements in a multiple array high density programmable logic device | Jerry D. Moench | 1997-01-14 |
| 5587921 | Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer | Michael J. Wright, Ju Shen | 1996-12-24 |
| 5586044 | Array of configurable logic blocks including cascadable lookup tables | Michael J. Wright, Ju Shen | 1996-12-17 |
| 5521529 | Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation | Bradley A. Sharpe-Geisler, Nicholas A. Schmitz, Bryon Irwin Moyer | 1996-05-28 |
| 5489857 | Flexible synchronous/asynchronous cell structure for a high density programmable logic device | Kerry A. Ilgenstein | 1996-02-06 |
| 5490074 | Constant delay interconnect for coupling configurable logic blocks | Michael J. Wright, Ju Shen | 1996-02-06 |
| 5485104 | Logic allocator for a programmable logic device | Jerry D. Moench, Kerry A. Ilgenstein | 1996-01-16 |
| 5469368 | Array of configurable logic blocks each including a first lookup table output coupled to selectively replace an output of second lookup with an alternate function output | Michael J. Wright, Ju Shen | 1995-11-21 |
| 5457409 | Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices | Jerry D. Moench, Kerry A. Ilgenstein | 1995-10-10 |
| 5436514 | High speed centralized switch matrix for a programmable logic device | Jerry D. Moench | 1995-07-25 |
| 5426335 | Pinout architecture for a family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix | Kerry A. Ingenstein | 1995-06-20 |
| 5422823 | Programmable gate array device having cascaded means for function definition | Michael J. Wright, Ju Shen | 1995-06-06 |
| 5359536 | Programmable gate array with improved interconnect structure, input/output structure and configurable logic block | Michael J. Wright, Ju Shen | 1994-10-25 |
| 5349544 | Programmable system synchronizer | Michael J. Wright | 1994-09-20 |
| 5349670 | Integrated circuit programmable sequencing element apparatus | Arthur H. Khu, Kapil Shankar | 1994-09-20 |
| 5329460 | Programmable gate array with improved interconnect structure, input/output structure and configurable logic block | Michael J. Wright, Ju Shen | 1994-07-12 |
| 5261116 | Programmable, expandable controller with flexible I/O | — | 1993-11-09 |
| 5260881 | Programmable gate array with improved configurable logic block | Michael J. Wright, Ju Shen | 1993-11-09 |
| 5255203 | Interconnect structure for programmable logic device | Michael J. Wright | 1993-10-19 |
| 5247195 | PLDs with high drive capability | John E. Turner | 1993-09-21 |
| 5239213 | Precision timing control programmable logic device | Robert Norman, Sai-Keung Lee | 1993-08-24 |
| 5233539 | Programmable gate array with improved interconnect structure, input/output structure and configurable logic block | Michael J. Wright, Ju Shen | 1993-08-03 |
| 5231588 | Programmable gate array with logic cells having symmetrical input/output structures | Michael J. Wright | 1993-07-27 |