Issued Patents All Time
Showing 76–100 of 143 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6150842 | Variable grain architecture for FPGA integrated circuits | Herman M. Chang, Bradley A. Sharpe-Geisler, Giap H. Tran | 2000-11-21 |
| 6130551 | Synthesis-friendly FPGA architecture with variable length and variable timing interconnect | Herman M. Chang, Bradley A. Sharpe-Geisler, Giap H. Tran, Bai Nguyen | 2000-10-10 |
| 6128770 | Configurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block) | Michael J. Wright, Ju Shen | 2000-10-03 |
| 6127843 | Dual port SRAM memory for run time use in FPGA integrated circuits | Herman M. Chang, Bradley A. Sharpe-Geisler, Bai Nguyen | 2000-10-03 |
| 6124730 | Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources | Bradley A. Sharpe-Geisler, Herman M. Chang, Bai Nguyen, Giap H. Tran | 2000-09-26 |
| 6107823 | Programmable control multiplexing for input/output blocks (IOBs) in FPGA integrated circuits | Bradley A. Sharpe-Geisler, Giap H. Tran | 2000-08-22 |
| 6102963 | Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD's | — | 2000-08-15 |
| 6100715 | Methods for configuring FPGA's having variable grain blocks and logic for providing time-shared access to interconnect resources | Bradley A. Sharpe-Geisler, Herman M. Chang, Bai Nguyen, Giap H. Tran | 2000-08-08 |
| 6097212 | Variable grain architecture for FPGA integrated circuits | Herman M. Chang, Bradley A. Sharpe-Geisler, Giap H. Tran | 2000-08-01 |
| 6097664 | Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan | Bai Nguyen, Bradley A. Sharpe-Geisler, Herman M. Chang | 2000-08-01 |
| 6081473 | FPGA integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode | Herman M. Chang, Bradley A. Sharpe-Geisler, Bai Nguyen | 2000-06-27 |
| 6034544 | Programmable input/output block (IOB) in FPGA integrated circuits | Herman M. Chang, Bradley A. Sharpe-Geisler, Bai Nguyen | 2000-03-07 |
| 6028446 | Flexible synchronous and asynchronous circuits for a very high density programmable logic device | Kerry A. Ilgenstein | 2000-02-22 |
| 5990702 | Flexible direct connections between input/output blocks (IOBs) and variable grain blocks (VGBs) in FPGA integrated circuits | Bradley A. Sharpe-Geisler, Giap H. Tran | 1999-11-23 |
| 5982193 | Input/output block (IOB) connections to MaxL lines, nor lines and dendrites in FPGA integrated circuits | Bradley A. Sharpe-Geisler, John Tobey, Giap H. Tran | 1999-11-09 |
| 5869981 | High density programmable logic device | George Landers, Nicholas A. Schmitz, Jerry D. Moench, Kerry A. Ilgenstein | 1999-02-09 |
| 5818254 | Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices | Bradley A. Sharpe-Geisler | 1998-10-06 |
| 5811986 | Flexible synchronous/asynchronous cell structure for a high density programmable logic device | Kerry A. Ilgenstein | 1998-09-22 |
| 5789939 | Method for providing a plurality of hierarchical signal paths in a very high-density programmable logic device | Bradley A. Sharpe-Geisler | 1998-08-04 |
| 5781030 | Programmable uniform symmetrical distribution logic allocator for a high-density complex PLD | Bradley A. Sharpe-Geisler | 1998-07-14 |
| 5764078 | Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix | Jerry D. Moench | 1998-06-09 |
| 5740069 | Logic device (PLD) having direct connections between configurable logic blocks (CLBs) and configurable input/output blocks (IOBs) | Michael J. Wright, Ju Shen | 1998-04-14 |
| 5644496 | Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses | Michael J. Wright | 1997-07-01 |
| 5621650 | Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses | Michael J. Wright | 1997-04-15 |
| 5617042 | Multiple array programmable logic device with a plurality of programmable switch matrices | — | 1997-04-01 |