Issued Patents All Time
Showing 26–50 of 143 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7327160 | SERDES with programmable I/O architecture | Jock Tomlinson, Kuang Chi, Ji-Cheng Zhao, Ju Shen, Jinghui Zhu | 2008-02-05 |
| 7295035 | Programmable logic device with enhanced logic block architecture | Manish Garg, Chan-Chi Jason Cheng, Satwant Singh, Ju Shen | 2007-11-13 |
| 7256613 | Programmable interconnect architecture for programmable logic devices | Brad Sharpe-Geisler, Cindy Lee | 2007-08-14 |
| 7215139 | Upgradeable and reconfigurable programmable logic device | Howard Tang, Jack T. Wong | 2007-05-08 |
| 7208975 | SERDES with programmable I/O architecture | Jock Tomlinson, Kuang Chi, Ji-Cheng Zhao, Ju Shen, Jinghui Zhu | 2007-04-24 |
| RE39510 | FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections | Herman M. Chang, Bradley A. Sharpe-Geisler, Bai Nguyen | 2007-03-13 |
| 7154298 | Block-oriented architecture for a programmable interconnect circuit | Jinghui Zhu | 2006-12-26 |
| 7098685 | Scalable serializer-deserializer architecture and programmable interface | Bai Nguyen, Kuang Chi, Brad Sharpe-Geisler, Giap H. Tran | 2006-08-29 |
| 7088134 | Programmable logic device with flexible memory allocation and routing | Jason Michael Cheng, Paul Bonwick, Bradley Felton, Andrew Armitage | 2006-08-08 |
| 7081771 | Upgradeable and reconfigurable programmable logic device | Howard Tang, Jack T. Wong | 2006-07-25 |
| 7061269 | I/O buffer architecture for programmable devices | Giap H. Tran, Bai Nguyen, Kiet Truong | 2006-06-13 |
| 7034599 | Clock generator with skew control | Hans Klein, Geoffrey R. Rickard, Harald Weller | 2006-04-25 |
| 7028281 | FPGA with register-intensive architecture | Bradley A. Sharpe-Geisler | 2006-04-11 |
| 7019577 | Clock generator | Hans Klein | 2006-03-28 |
| 7000212 | Hierarchical general interconnect architecture for high density FPGA'S | Bradley A. Sharpe-Geisler | 2006-02-14 |
| 6922078 | Programmable logic device with enhanced wide and deep logic capability | — | 2005-07-26 |
| 6919736 | Field programmable gate array having embedded memory with configurable depth and width | Bradley A. Sharpe-Geisler, Bai Nguyen, Yu-Hua Huang, Jack T. Wong | 2005-07-19 |
| 6885227 | Clock generator with skew control | Hans Klein, Geoffrey R. Rickard, Harald Weller | 2005-04-26 |
| 6879182 | CPLD with multi-function blocks and distributed memory | Chan-Chi Jason Cheng | 2005-04-12 |
| 6864713 | Multi-stage interconnect architecture for complex programmable logic devices | Paul Bonwick | 2005-03-08 |
| 6861871 | Cascaded logic block architecture for complex programmable logic devices | Paul Bonwick, Chan-Chi Jason Cheng | 2005-03-01 |
| 6861868 | High speed interface for a programmable interconnect circuit | Jinghui Zhu, Kuang Chi, Chienkuang Chen | 2005-03-01 |
| 6838904 | Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation | Fabiano Fontana, Gilles Bosco | 2005-01-04 |
| 6828823 | Non-volatile and reconfigurable programmable logic devices | Cyrus Y. Tsui, Benny Ma, Ju Shen, Sam Tsai, Jack T. Wong +1 more | 2004-12-07 |
| 6753696 | Programmable optimized-distribution logic allocator for a high-density complex PLD | Bradley A. Sharpe-Geisler, Nicholas A. Schmitz | 2004-06-22 |