Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12063780 | Memory cell structure of a three-dimensional memory device | Xiaowang Dai, Zhenyu Lu, Jun Chen, Qian Tao, Yushi Hu +4 more | 2024-08-13 |
| 11133325 | Memory cell structure of a three-dimensional memory device | Xiaowang Dai, Zhenyu Lu, Jun Chen, Qian Tao, Yushi Hu +4 more | 2021-09-28 |
| 11114439 | Multi-division 3D NAND memory device | Zhong Zhang | 2021-09-07 |
| 10971199 | Microcontroller for non-volatile memory with combinational logic | Pao-Ling Koh, Yuheng Zhang | 2021-04-06 |
| 10847528 | Memory cell structure of a three-dimensional memory device | Xiaowang Dai, Zhenyu Lu, Jun Chen, Qian Tao, Yushi Hu +4 more | 2020-11-24 |
| 10825826 | Three-dimensional memory device having bonding structures connected to bit lines and methods of making the same | Jixin Yu, Tae Kyung Kim, Johann Alsmeier, Jian Chen | 2020-11-03 |
| 10811058 | Bonded assembly containing memory die bonded to integrated peripheral and system die and methods for making the same | Yanli Zhang, Zhixin Cui, Akio Nishida, Johann Alsmeier, Steven T. Sprouse | 2020-10-20 |
| 10790285 | Multi-division 3D NAND memory device | Zhong Zhang | 2020-09-29 |
| 10707228 | Three-dimensional memory device having bonding structures connected to bit lines and methods of making the same | Jixin Yu, Tae Kyung Kim, Johann Alsmeier, Jian Chen | 2020-07-07 |
| 10644015 | Memory cell structure of a three-dimensional memory device | Xiaowang Dai, Zhenyu Lu, Jun Chen, Qian Tao, Yushi Hu +4 more | 2020-05-05 |
| 10256248 | Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof | Zhenyu Lu, Jixin Yu, Johann Alsmeier, Fumiaki Toyama, Yuki Mizutani +5 more | 2019-04-09 |
| 10249640 | Within-array through-memory-level via structures and method of making thereof | Jixin Yu, Zhenyu Lu, Alexander Chu, Kensuke Yamaguchi, Hiroyuki Ogawa +2 more | 2019-04-02 |
| 10120816 | Bad column management with data shuffle in pipeline | Wanfang Tsai | 2018-11-06 |
| 10121522 | Sense circuit with two sense nodes for cascade sensing | Tai-Yuan Tseng, Anirudh Amarnath | 2018-11-06 |