Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10860319 | Apparatus and method for an early page predictor for a memory paging subsystem | Mark Dechene, Manjunath Shevgoor, Faruk Guvenilir, Jonathan Christopher Perry | 2020-12-08 |
| 10853078 | Method and apparatus for supporting speculative memory optimizations | Vineeth Mekkat, Mark Dechene, John W. Faistl, Janghaeng Lee, Hou-Jen Ko +2 more | 2020-12-01 |
| 10228956 | Supporting binary translation alias detection in an out-of-order processor | Vineeth Mekkat, Mark Dechene, Jason M. Agron, Sebastian Winkel | 2019-03-12 |
| 9336156 | Method and apparatus for cache line state update in sectored cache with line state tracker | Erik G. Hallnor, Stanley S. Kulick, Jeffrey L. Miller | 2016-05-10 |
| 9311241 | Method and apparatus to write modified cache data to a backing store while retaining write permissions | Ravi Rajwar, Robert S. Chappell, Jason Anthony Bessette | 2016-04-12 |
| 9298632 | Hybrid cache state and filter tracking of memory operations during a transaction | Robert S. Chappell, Ravi Rajwar, Jason Anthony Bessette | 2016-03-29 |
| 7603527 | Resolving false dependencies of speculative load instructions | Sebastien Hily, Per Hammarlund | 2009-10-13 |
| 6922745 | Method and apparatus for handling locks | Harish Kumar, Aravindh Baktha, Mike Upton, KS Venkatraman, Herbert Hum | 2005-07-26 |
| 6370625 | Method and apparatus for lock synchronization in a microprocessor system | Douglas M. Carmean, Harish Kumar, Brent E. Lince, Michael D. Upton | 2002-04-09 |