Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11908857 | Semiconductor devices having late-formed isolation structures | Haiting Wang, Sipeng Gu | 2024-02-20 |
| 11812670 | Memory device comprising a top via electrode and methods of making such a memory device | Haiting Wang, Sipeng Gu | 2023-11-07 |
| 11785860 | Top electrode for a memory device and methods of making such a memory device | Sipeng Gu, Haiting Wang | 2023-10-10 |
| 11721728 | Self-aligned contact | Sipeng Gu, Jiehui Shu, Halting Wang | 2023-08-08 |
| 11569437 | Memory device comprising a top via electrode and methods of making such a memory device | Halting Wang, Sipeng Gu | 2023-01-31 |
| 11502200 | Transistor device having sidewall spacers contacting lower surfaces of an epitaxial semiconductor material | Sipeng Gu, Judson R. Holt, Haiting Wang | 2022-11-15 |
| 11482456 | Forming two portion spacer after metal gate and contact formation, and related IC structure | Hui Zang, Jiehui Shu | 2022-10-25 |
| 11437568 | Memory device and methods of making such a memory device | Haiting Wang, Sipeng Gu | 2022-09-06 |
| 11342453 | Field effect transistor with asymmetric gate structure and method | Haiting Wang, Zhiqing Li | 2022-05-24 |
| 11264504 | Active and dummy fin structures | Haiting Wang, Hong Yu | 2022-03-01 |
| 11239336 | Integrated circuit structure with niobium-based silicide layer and methods to form same | Wei Hong, Domingo A. Ferrer, Hong Yu | 2022-02-01 |
| 11222844 | Via structures for use in semiconductor devices | Jun Lian, Sipeng Gu, Haiting Wang | 2022-01-11 |
| 11171237 | Middle of line gate structures | Halting Wang, Hui Zang, Jiehui Shu | 2021-11-09 |
| 11164794 | Semiconductor structures in a wide gate pitch region of semiconductor devices | Wei Hong, Liu Jiang | 2021-11-02 |
| 11094827 | Semiconductor devices with uniform gate height and method of forming same | Xiaoxiao Zhang, Shesh Mani Pandey, Hui Zang | 2021-08-17 |
| 10833171 | Spacer structures on transistor devices | Jiehui Shu, Hui Zang | 2020-11-10 |
| 10818498 | Shaped gate caps in spacer-lined openings | Haiting Wang, Hui Zang | 2020-10-27 |
| 10811422 | Semiconductor recess to epitaxial regions and related integrated circuit structure | Wei Hong, Hui Zang, David Paul Brunco | 2020-10-20 |
| 10700173 | FinFET device with a wrap-around silicide source/drain contact structure | Yi Qi, Hsien-Ching Lo, Hong Yu, Wei Hong, Xing Zhang +4 more | 2020-06-30 |
| 10636894 | Fin-type transistors with spacers on the gates | Hui Zang, Hsien-Ching Lo, Qun Gao, Jerome Ciavatti, Yi Qi +4 more | 2020-04-28 |
| 10553707 | FinFETs having gates parallel to fins | Hui Zang, Bingwu Liu, Manoj Joshi, Jae Gon Lee, Hsien-Ching Lo +1 more | 2020-02-04 |
| 10461155 | Epitaxial region for embedded source/drain region having uniform thickness | Yoong Hooi Yong, Hsien-Ching Lo, Xusheng Wu, Joo Tat Ong, Wei Hong +6 more | 2019-10-29 |
| 10249538 | Method of forming vertical field effect transistors with different gate lengths and a resulting structure | Yi Qi, Hsien-Ching Lo, Jianwei Peng, Wei Hong, Yongjun Shi +5 more | 2019-04-02 |
| 10164010 | Finfet diffusion break having protective liner in fin insulator | Wei Hong, Hsien-Ching Lo, Haiting Wang, Yi Qi, Yongjun Shi +2 more | 2018-12-25 |
| 10068902 | Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method | Hui Zang, Hsien-Ching Lo, Yongjun Shi, Randy W. Mann, Yi Qi +4 more | 2018-09-04 |