Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7694269 | Method for positioning sub-resolution assist features | Nagaraj Savithri, Mark E. Mason | 2010-04-06 |
| 7458058 | Verifying a process margin of a mask pattern using intermediate stage models | Ashesh Parikh, Thomas J. Aton | 2008-11-25 |
| 7402514 | Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer | Robert Tsu, Joe W. McPherson, Thomas D. Bonifield | 2008-07-22 |
| 7323727 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, Jeffrey E. Koelling, Troy H. Herndon | 2008-01-29 |
| 7211842 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, Jeffrey E. Koelling, Troy H. Herndon | 2007-05-01 |
| 6967371 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, Jeffrey E. Koelling, Troy H. Herndon | 2005-11-22 |
| 6831317 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, Jeffrey E. Koelling, Troy H. Herndon | 2004-12-14 |
| 6815742 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, Jeffrey E. Koelling, Troy H. Herndon | 2004-11-09 |
| 6653676 | Integrated circuit capacitor | Robert Tsu, Isamu Asano, Shinpei Iijima | 2003-11-25 |
| 6559050 | Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devices | Jiong-Ping Lu, Ming-Jang Hwang, Dirk N. Anderson, Wei William Lee | 2003-05-06 |
| 6528888 | Integrated circuit and method | Chih-Chen Cho, Jeffrey McKee, Isamu Asano, Robert Tsu | 2003-03-04 |
| 6512257 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, Jeffrey E. Koelling, Troy H. Herndon | 2003-01-28 |
| 6461955 | Yield improvement of dual damascene fabrication through oxide filling | Robert Tsu, Qi-Zhong Hong | 2002-10-08 |
| 6396088 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, Jeffrey E. Koelling, Troy H. Herndon | 2002-05-28 |
| 6294420 | Integrated circuit capacitor | Robert Tsu, Isamu Asano, Shinpei Iijima | 2001-09-25 |
| 6288925 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, Jeffrey E. Koelling, Troy H. Herndon | 2001-09-11 |
| 6261884 | Method of fabricating and operating single polysilicon flash EEPROM with low positive programming and erasing voltage and small cell size | Chi-Chien Ho | 2001-07-17 |
| 6239479 | Thermal neutron shielded integrated circuits | Ming-Jang Hwang, Robert Baumann | 2001-05-29 |
| 6218311 | Post-etch treatment of a semiconductor device | Jeffrey McKee, Ming-Jang Hwang, Chih-Chen Cho | 2001-04-17 |
| 6115279 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, Jeffrey E. Koelling, Troy H. Herndon | 2000-09-05 |
| 6100588 | Multiple level conductor wordline strapping scheme | Hugh P. McAdams | 2000-08-08 |
| 6096597 | Method for fabricating an integrated circuit structure | Robert Tsu, Shimpei Iijima, Isamu Asano, Masato Kunitomo, Tsuyoshi Tamaru | 2000-08-01 |
| 6069813 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, Jeffrey E. Koelling, Troy H. Herndon | 2000-05-30 |
| 6060354 | In-situ doped rough polysilicon storage cell structure formed using gas phase nucleation | Robert Tsu, Ming-Jang Hwang | 2000-05-09 |
| 6054732 | Single polysilicon flash EEPROM with low positive programming and erasing voltage and small cell size | Chi-Chien Ho | 2000-04-25 |