Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12020124 | Selecting optimum primary and secondary parameters to calibrate and generate an unbiased forecasting model | Afzal Husain, Suresh Aswathnarayana, Paolo Astro, Mercedes Monroy | 2024-06-25 |
| 11775852 | Network optimization | Afzal Husain, Alon Arad, Suresh Aswathnarayana, Ragnar-Miguel Myhrer, Tejas Rao +3 more | 2023-10-03 |
| 10339251 | Method to improve transistor matching | Chi-Chien Ho, Thomas John Smelko, Rajni J. Aggarwal | 2019-07-02 |
| 9853086 | CMOS-based thermopile with reduced thermal conductance | Henry Litzmann Edwards, Toan Tran, Jeffrey R. Debord, Bradley David Sucher | 2017-12-26 |
| 9665675 | Method to improve transistor matching | Chi-Chien Ho, Thomas John Smelko, Rajni J. Aggarwal | 2017-05-30 |
| 9496313 | CMOS-based thermopile with reduced thermal conductance | Henry Litzmann Edwards, Toan Tran, Jeffrey R. Debord, Bradley David Sucher | 2016-11-15 |
| 8806388 | Extraction of imaging parameters for computational lithography using a data weighting algorithm | — | 2014-08-12 |
| 8793626 | Computational lithography with feature upsizing | Chi-Chien Ho, Thomas John Smelko | 2014-07-29 |
| 8394681 | Transistor layout for manufacturing process control | Anand Seshadri | 2013-03-12 |
| 8015513 | OPC models generated from 2D high frequency test patterns | Willie J. Yarbrough | 2011-09-06 |
| 7985990 | Transistor layout for manufacturing process control | Anand Seshadri | 2011-07-26 |
| 7842955 | Carbon nanotube transistors on a silicon or SOI substrate | Andrew Marshall | 2010-11-30 |
| 7772059 | Method for fabricating graphene transistors on a silicon or SOI substrate | Andrew Marshall | 2010-08-10 |
| 7687308 | Method for fabricating carbon nanotube transistors on a silicon or SOI substrate | Andrew Marshall | 2010-03-30 |
| 7562333 | Method and process for generating an optical proximity correction model based on layout density | Jarvis Benjamin Jacobs | 2009-07-14 |
| 7458058 | Verifying a process margin of a mask pattern using intermediate stage models | William R. McKee, Thomas J. Aton | 2008-11-25 |