Issued Patents All Time
Showing 25 most recent of 104 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430128 | Sharing register file usage between fused processing resources | Varghese George, Joydeep Ray, Ashutosh Garg, Jorge Parra, Shubh Shah +1 more | 2025-09-30 |
| 12399685 | Systolic array having support for output sparsity | Jorge Parra, Fangwen Fu, Varghese George, Mike B. Macpherson, Supratim Pal +6 more | 2025-08-26 |
| 12346694 | Register file for systolic array | Chandra Gurram, Wei-Yu Chen, Fangwen Fu, Sabareesh Ganapathy, Varghese George +4 more | 2025-07-01 |
| 12333306 | High performance constant cache and constant access mechanisms | Sudarshanram Shetty, Travis T. Schluessler, Guei-Yuan Lueh, PingHang Cheung, Srividya Karumuri +3 more | 2025-06-17 |
| 12229581 | Virtualization and multi-tenancy support in graphics processors | Rajesh M. Sankaran, Bret L. Toll, William C. Rash, Gang Chen, Varghese George | 2025-02-18 |
| 12190406 | Pointer de-referencing technologies | Raghavendra Kamath Miyar, Rajalakshmi Athimoolam, Jorge F. Garcia Pabon, Rajarshi Bajpayee, Krishan Malik | 2025-01-07 |
| 12174783 | Systolic array of arbitrary physical and logical depth | Jorge Parra, Wei-Yu Chen, Kaiyu Chen, Varghese George, Junjie Gu +4 more | 2024-12-24 |
| 12164884 | Tanh and sigmoid function execution | Shuai Mu, Cristina S. Anderson | 2024-12-10 |
| 12067394 | Native support for execution of get exponent, get mantisssa, and scale instructions within a graphics processing unit via reuse of fused multiply-add execution unit hardware logic | Shuai Mu, Cristina S. Anderson | 2024-08-20 |
| 12039001 | Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs | Jorge Parra, Supratim Pal, Ashutosh Garg, Shubra Marwaha, Chandra Gurram +3 more | 2024-07-16 |
| 12007935 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra, Chandra Gurram +3 more | 2024-06-11 |
| 12008067 | Sparse matrix multiplication acceleration mechanism | Mathew Nevin, Jorge Parra, Ashutosh Garg, Shubra Marwaha, Shubh Shah | 2024-06-11 |
| 11954063 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra, Chandra Gurram +3 more | 2024-04-09 |
| 11934797 | Mechanism to perform single precision floating point extended math operations | Abhishek Rhisheekesan, Shashank Lakshminarayana | 2024-03-19 |
| 11900502 | Compiler assisted register file write reduction | Chandra Gurram, Gang Chen, Supratim Pal, Ashutosh Garg, Jorge Parra +3 more | 2024-02-13 |
| 11900114 | Systems and methods to skip inconsequential matrix operations | Elmoustapha Ould-Ahmed-Vall, William C. Rash, Varghese George, Rajesh M. Sankaran | 2024-02-13 |
| 11709793 | Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format | Shubra Marwaha, Ashutosh Garg, Supratim Pal, Jorge Parra, Chandra Gurram +3 more | 2023-07-25 |
| 11669329 | Instructions and logic for vector multiply add with zero skipping | Supratim Pal, Sasikanth Avancha, Ishwar Bhati, Wei-Yu Chen, Dipankar Das +7 more | 2023-06-06 |
| 11640297 | Instruction and logic for systolic dot product with accumulate | Guei-Yuan Lueh, Supratim Pal, Ashutosh Garg, Chandra Gurram, Jorge Parra +10 more | 2023-05-02 |
| 11636174 | Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs | Jorge Parra, Supratim Pal, Ashutosh Garg, Shubra Marwaha, Chandra Gurram +3 more | 2023-04-25 |
| 11625244 | Native support for execution of get exponent, get mantissa, and scale instructions within a graphics processing unit via reuse of fused multiply-add execution unit hardware logic | Shuai Mu, Cristina S. Anderson | 2023-04-11 |
| 11593069 | Use of a single instruction set architecture (ISA) instruction for vector normalization | Abhishek Rhisheekesan, Supratim Pal, Shashank Lakshminarayana | 2023-02-28 |
| 11579878 | Register sharing mechanism to equally allocate disabled thread registers to active threads | Pratik J. Ashar, Supratim Pal, Wei-Yu Chen, Guei-Yuan Lueh | 2023-02-14 |
| 11494163 | Conversion hardware mechanism | Naveen Mellempudi, Dipankar Das, Chunhui Mei, Kristopher Wong, Dhiraj D. Kalamkar +2 more | 2022-11-08 |
| 11403097 | Systems and methods to skip inconsequential matrix operations | Elmoustapha Ould-Ahmed-Vall, William C. Rash, Varghese George, Rajesh M. Sankaran | 2022-08-02 |