SC

Suresh Chittor

IN Intel: 17 patents #2,418 of 30,777Top 8%
Overall (All Time): #247,831 of 4,157,543Top 6%
18
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12405904 Sharing memory and I/O services between nodes Debendra Das Sharma, Robert G. Blankenship, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen +2 more 2025-09-02
11567877 Memory utilized as both system memory and near memory Rajat Agarwal, Wei-Pin Chen 2023-01-31
11250902 Method and apparatus to reduce power consumption for refresh of memory devices on a memory module Douglas Heymann, Wei-Pin Chen, George Vergis 2022-02-15
11216386 Techniques for setting a 2-level auto-close timer to access a memory device Vivek Kozhikkottu, Esha Choukse, Shankar Ganesh Ramasubramanian 2022-01-04
10936507 System, apparatus and method for application specific address mapping Vivek Kozhikkottu, Esha Choukse, Shankar Ganesh Ramasubramanian, Melin Dadual 2021-03-02
10915468 Sharing memory and I/O services between nodes Debendra Das Sharma, Robert G. Blankenship, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen +2 more 2021-02-09
7991875 Link level retry scheme Ching-Tsun Chou, Andalib Khan, Akhilesh Kumar, Phanindra Kumar Mannava, Rajee Ram +3 more 2011-08-02
7734980 Mitigating silent data corruption in a buffered memory module architecture James W. Alexander, Dennis W. Brzezinski, Kai Cheng, Rajat Agarwal 2010-06-08
7644347 Silent data corruption mitigation using error correction code with embedded signaling fault detection James W. Alexander, Dennis W. Brzezinski, Kai Cheng, Henk G. Neefs, Rajat Agarwal 2010-01-05
7486685 System for sharing channels by interleaving flits Linda J. Rankin 2009-02-03
7016304 Link level retry scheme Ching-Tsun Chou, Andalib Khan, Akhilesh Kumar, Phanindra Kumar Mannava, Rajee Ram +3 more 2006-03-21
6298420 Coherent variable length reads from system memory Chih-Cheh Chen, Sin S. Tan, Jonathan Spitz 2001-10-02
6195722 Method and apparatus for deferring transactions on a host bus having a third party agent Rajee Ram, Lily P. Looi, David R. Jackson 2001-02-27
6145062 Selective conflict write flush Suneeta Sah, Prantik K. Nag, Joseph Ku 2000-11-07
6061764 Coherent variable length reads which implicates multiple cache lines by a memory controller connected to a serial and a pipelined bus utilizing a plurality of atomic transactions Chih-Cheh Chen, Sin S. Tan, Jonathan Spitz 2000-05-09
6021457 Method and an apparatus for minimizing perturbation while monitoring parallel applications David W. Archer, Don Breazeal, Richard J. Greco, Wayne Duncan Smith, Jim Sutton 2000-02-01
5987552 Bus protocol for atomic transactions Suvansh Krishan Kapur, Lily P. Looi 1999-11-16
5592610 Method and apparatus for enhancing the fault-tolerance of a network 1997-01-07