Issued Patents All Time
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10859627 | In-field system testing | Sreejit Chakravarty, Oscar Mendoza, Ramasubramanian Rajamani, Bryan J. Gran, Neel Shah +3 more | 2020-12-08 |
| 10491381 | In-field system test security | Neel Shah, Kirk S. Yap, Amy L. Santoni, Michael Neve de Mevergnies, Oscar Mendoza +3 more | 2019-11-26 |
| 9654143 | Consecutive bit error detection and correction | Guillem Sole, Roger Espasa, Brian J. Hickmann, Wei Wu, Thomas D. Fletcher | 2017-05-16 |
| 9110768 | Residue based error detection for integer and floating point execution units | — | 2015-08-18 |
| 8412981 | Core sparing on multi-core platforms | Alberto J. Munoz | 2013-04-02 |
| 7996663 | Saving and restoring architectural state for processor cores | Paul M. Stillwell, Jr., Moenes Zaher Iskarous | 2011-08-09 |
| 7769795 | End-to-end residue-based protection of an execution pipeline that supports floating point operations | — | 2010-08-03 |
| 7555692 | End-to-end residue based protection of an execution pipeline | — | 2009-06-30 |
| 7543007 | Residue-based error detection for a shift operation | — | 2009-06-02 |
| 7487296 | Multi-stride prefetcher with a recurring prefetch table | Sudarshan Kadambi, Yuan C. Chou | 2009-02-03 |
| 7418582 | Versatile register file design for a multi-threaded processor utilizing different modes and register windows | Daniel Leibholz, David Greenhill | 2008-08-26 |
| 7340590 | Handling register dependencies between instructions specifying different width registers | Rabin Sugumar, Chandra Thimmannagari | 2008-03-04 |
| 7325101 | Techniques for reducing off-chip cache memory accesses | Paul N. Loewenstein | 2008-01-29 |
| 7219218 | Vector technique for addressing helper instruction groups associated with complex instructions | Chandra Thimmannagari, Rabin Sugumar | 2007-05-15 |
| 7191316 | Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction stream | Rabin Sugumar, Robert Nuckolls, Chandra Thimmannagari | 2007-03-13 |
| 7124284 | Method and apparatus for processing a complex instruction for execution and retirement | Rabin Sugumar, Chandra Thimmannagari | 2006-10-17 |
| 7080237 | Register window flattening logic for dependency checking among instructions | Chandra Thimmannagari, Rabin Sugumar, Robert Nuckolls | 2006-07-18 |
| 7065635 | Method for handling condition code modifiers in an out-of-order multi-issue multi-stranded processor | Rabin Sugumar, Chandra Thimmannagari | 2006-06-20 |
| 7043609 | Method and apparatus for protecting a state associated with a memory structure | Victor Melamed | 2006-05-09 |
| 7035999 | Register window fill technique for retirement window having entry size less than amount of fill instructions | Chandra Thimmanagari, Rabin Sugumar, Robert Nuckolls | 2006-04-25 |
| 7024541 | Register window spill technique for retirement window having entry size less than amount of spill instructions | Chandra Thimmanagari, Rabin Sugumar, Robert Nuckolls | 2006-04-04 |
| 6820086 | Forming linked lists using content addressable memory | William R. Bryg, Joseph H. Hassoun | 2004-11-16 |
| 6704876 | Microprocessor speed control mechanism using power dissipation estimation based on the instruction data path | Ronald J. Melanson | 2004-03-09 |
| 6453427 | Method and apparatus for handling data errors in a computer system | Nhon Quach, John Fu, James O. Hays, Valentin Anders, Alberto J. Munoz +1 more | 2002-09-17 |
| 6185660 | Pending access queue for providing data to a target register during an intermediate pipeline phase after a computer cache miss | Dean Mulla | 2001-02-06 |