Issued Patents All Time
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10861852 | Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) for complementary metal-oxide semiconductor (CMOS) cell circuits | Xia Li, Periannan Chidambaram | 2020-12-08 |
| 10490558 | Reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells | Youn Sung Choi, Samit Sengupta | 2019-11-26 |
| 10304957 | FinFET with reduced series total resistance | Ukjin Roh | 2019-05-28 |
| 10062768 | Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout | Youn Sung Choi, Ukjin Roh | 2018-08-28 |
| 10008499 | Method to form silicide and contact at embedded epitaxial facet | Kwan-Yong Lim, James Walter Blatchford, Younsung Choi | 2018-06-26 |
| 9947765 | Dummy gate placement methodology to enhance integrated circuit performance | Younsung Choi, Gregory Charles Baldwin | 2018-04-17 |
| 9922971 | Integration of analog transistor | Himadri Sekhar Pal, Youn Sung Choi | 2018-03-20 |
| 9882051 | Fin field effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions | Ukjin Roh, Youn Sung Choi | 2018-01-30 |
| 9812452 | Method to form silicide and contact at embedded epitaxial facet | Kwan-Yong Lim, James Walter Blatchford, Younsung Choi | 2017-11-07 |
| 9634138 | Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout | Youn Sung Choi, Ukjin Roh | 2017-04-25 |
| 9508601 | Method to form silicide and contact at embedded epitaxial facet | Kwan-Yong Lim, James Walter Blatchford, Younsung Choi | 2016-11-29 |
| 9496142 | Dummy gate placement methodology to enhance integrated circuit performance | Younsung Choi, Gregory Charles Baldwin | 2016-11-15 |
| 9412741 | Integration of analog transistor | Himadri Sekhar Pal, Youn Sung Choi | 2016-08-09 |
| 9406769 | Silicide formation due to improved SiGe faceting | Kwan-Yong Lim, Ebenezer E. Eshun, Youn Sung Choi | 2016-08-02 |
| 9224653 | Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and SRAM transistor yield | Himadri Sekhar Pal, Ebenezer E. Eshun | 2015-12-29 |
| 9202810 | Integration of analog transistor | Himadri Sekhar Pal, Youn Sung Choi | 2015-12-01 |
| 9202883 | Silicide formation due to improved SiGe faceting | Kwan-Yong Lim, Ebenezer E. Eshun, Youn Sung Choi | 2015-12-01 |
| 9136382 | Native devices having improved device characteristics and methods for fabrication | Rongtian Zhang | 2015-09-15 |
| 9093298 | Silicide formation due to improved SiGe faceting | Kwan-Yong Lim, Ebenezer E. Eshun, Youn Sung Choi | 2015-07-28 |
| 9076670 | Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and SRAM transistor yield | Himadri Sekhar Pal, Ebenezer E. Eshun | 2015-07-07 |
| 8748256 | Integrated circuit having silicide block resistor | Song Zhao, Gregory Charles Baldwin, Youn Sung Choi | 2014-06-10 |
| 8748253 | Memory and logic with shared cryogenic implants | — | 2014-06-10 |
| 8541269 | Native devices having improved device characteristics and methods for fabrication | Rongtian Zhang | 2013-09-24 |
| 8405154 | Low cost transistors using gate orientation and optimized implants | Kamel Benaissa, Greg Baldwin, Shaofeng Yu | 2013-03-26 |
| 8119470 | Mitigation of gate to contact capacitance in CMOS flow | Borna J. Obradovic, Lindsey Hall, Craig Huffman, Ajith Varghese | 2012-02-21 |