Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11737985 | Formulations comprising hydralazine, prazosin, torsemide, spironolactone, and/or naltrexone and treatments using same | — | 2023-08-29 |
| 11007203 | Formulations comprising aldosterone receptor antagonists and treatments using same | — | 2021-05-18 |
| 10942745 | Fast multi-width instruction issue in parallel slice processor | Salma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Dung Q. Nguyen, Tu-An T. Nguyen +1 more | 2021-03-09 |
| 10803224 | Propagating constants of structured soft blocks while preserving the relative placement structure | Rokesh Jayasundar, Shyam Ramji, Paul G. Villarrubia | 2020-10-13 |
| 10740107 | Operation of a multi-slice processor implementing load-hit-store handling | Salma Ayub, Joshua W. Bowman, Jeffrey C. Brownscheidle, Kurt A. Feiste, Dung Q. Nguyen +1 more | 2020-08-11 |
| 10719056 | Merging status and control data in a reservation station | Brian D. Barrick, Joshua W. Bowman, Jeffrey C. Brownscheidle, Sundeep Chadha, Michael J. Genden +2 more | 2020-07-21 |
| 10596119 | Methods of treatment comprising torsemide | — | 2020-03-24 |
| 10463622 | Treatments and formulations comprising Torsemide | — | 2019-11-05 |
| 10445100 | Broadcasting messages between execution slices for issued instructions indicating when execution results are ready | Salma Ayub, Joshua W. Bowman, Jeffrey C. Brownscheidle, Sundeep Chadha, Dhivya Jeganathan +2 more | 2019-10-15 |
| 10154963 | Controlled-release formulations comprising Torsemide | — | 2018-12-18 |
| 10120693 | Fast multi-width instruction issue in parallel slice processor | Salma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Dung Q. Nguyen, Tu-An T. Nguyen +1 more | 2018-11-06 |
| 10031757 | Operation of a multi-slice processor implementing a mechanism to overcome a system hang | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dhivya Jeganathan, Dung Q. Nguyen | 2018-07-24 |
| 9996359 | Fast multi-width instruction issue in parallel slice processor | Salma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Dung Q. Nguyen, Tu-An T. Nguyen +1 more | 2018-06-12 |
| 9983879 | Operation of a multi-slice processor implementing dynamic switching of instruction issuance order | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dhivya Jeganathan, Dung Q. Nguyen | 2018-05-29 |
| 9298420 | Identification of the bit position of a selected instance of a particular bit value in a binary bit string | Akif Ali, Aquilur Rahman | 2016-03-29 |
| 6389577 | Analyzing CMOS circuit delay | Visweswara Rao Kodali, Johnny LeBlanc, Kevin William McCauley | 2002-05-14 |
| 5905999 | Cache sub-array arbitration | Peichun Peter Liu, Rajinder Paul Singh | 1999-05-18 |
| 5825208 | Method and apparatus for fast evaluation of dynamic CMOS logic circuits | Howard Levy | 1998-10-20 |
| 5771186 | System and method for multiplying in a data processing system | Visweswara Rao Kodali | 1998-06-23 |
| 5737564 | Cache memory system having multiple caches with each cache mapped to a different area of main memory to avoid memory contention and to lessen the number of cache snoops | — | 1998-04-07 |
| 5724249 | System and method for power management in self-resetting CMOS circuitry | Visweswara Rao Kodali | 1998-03-03 |
| 5586298 | Effective use of memory bus in a multiprocessing environment by controlling end of data intervention by a snooping cache | — | 1996-12-17 |
| 5550490 | Single-rail self-resetting logic circuitry | Christopher McCall Durham, Visweswara Rao Kodali | 1996-08-27 |
| 5502828 | Reducing memory access in a multi-cache multiprocessing environment with each cache mapped into different areas of main memory to avoid contention | — | 1996-03-26 |
| 5206828 | Special carry save adder for high speed iterative division | Thomas W. Lynch | 1993-04-27 |