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Structure including hybrid plasmonic waveguide using metal silicide layer |
Yusheng Bian |
2025-07-29 |
| 12176351 |
Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor |
George R. Mulfinger, Yusheng Bian |
2024-12-24 |
| 11907685 |
Structure and method for random code generation |
Judson R. Holt, Julien Frougier, George R. Mulfinger, Daniel Jaeger |
2024-02-20 |
| 11650382 |
Optical components undercut by a sealed cavity |
Yusheng Bian, Takako Hirokawa |
2023-05-16 |
| 11610843 |
Well tap for an integrated circuit product and methods of forming such a well tap |
Hongru Ren, David Pritchard, Manjunatha Prabhu |
2023-03-21 |
| 11569268 |
Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor |
George R. Mulfinger, Yusheng Bian |
2023-01-31 |
| 11450573 |
Structure with different stress-inducing isolation dielectrics for different polarity FETs |
George R. Mulfinger, Chung Foong Tan |
2022-09-20 |
| 11409037 |
Enlarged waveguide for photonic integrated circuit without impacting interconnect layers |
Yusheng Bian, Karen A. Nummy |
2022-08-09 |
| 11217678 |
Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI |
George R. Mulfinger, Rick Carter, Peter Baars, Hans-Jürgen Thees, Jan Höntschel |
2022-01-04 |
| 11127843 |
Asymmetrical lateral heterojunction bipolar transistors |
Judson R. Holt, Alexander M. Derrickson, George R. Mulfinger, Alexander L. Martin, Jagar Singh |
2021-09-21 |
| 11094805 |
Lateral heterojunction bipolar transistors with asymmetric junctions |
Alexander M. Derrickson, Edmund K. Banghart, Alexander L. Martin, Jagar Singh, Katherina Babich +1 more |
2021-08-17 |
| 10943814 |
Etch stop member in buried insulator of SOI substrate to reduce contact edge punch through |
Jiehui Shu |
2021-03-09 |
| 10522655 |
Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI |
George R. Mulfinger, Rick Carter, Peter Baars, Hans-Jürgen Thees, Jan Höntschel |
2019-12-31 |
| 10326007 |
Post gate silicon germanium channel condensation and method for producing the same |
George R. Mulfinger, Timothy J. McArdle, Judson R. Holt |
2019-06-18 |
| 10217660 |
Technique for patterning active regions of transistor elements in a late manufacturing stage |
George R. Mulfinger |
2019-02-26 |
| 10056381 |
Punchthrough stop layers for fin-type field-effect transistors |
Amy L. Child, George R. Mulfinger |
2018-08-21 |
| 10050119 |
Method for late differential SOI thinning for improved FDSOI performance and HCI optimization |
George R. Mulfinger, Dina H. Triyoso |
2018-08-14 |
| 10043893 |
Post gate silicon germanium channel condensation and method for producing the same |
George R. Mulfinger, Timothy J. McArdle, Judson R. Holt |
2018-08-07 |
| 9875936 |
Spacer defined fin growth and differential fin width |
Rohit Pal, Jeremy A. Wahl |
2018-01-23 |
| 9806170 |
Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI |
George R. Mulfinger, Rick Carter, Peter Baars, Hans-Jürgen Thees, Jan Höntschel |
2017-10-31 |
| 9634143 |
Methods of forming FinFET devices with substantially undoped channel regions |
Jeremy A. Wahl |
2017-04-25 |
