Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12170478 | Merged power delivery | Alexander B. Uan-Zo-Li, Shuai Jiang, Jamie L. Langlinais, Per Hammarlund, Hans Lee Yeager +7 more | 2024-12-17 |
| 11076493 | Implementing high-speed signaling via dedicated printed circuit-board media | Douglas A. Baska, Daniel M. Dreps, Roger D. Weekly | 2021-07-27 |
| 11069665 | Trimmable banked capacitor | Vidhya Ramachandran, Chonghua Zhong, Jun Zhai, Long Huang, Mengzhi Pang | 2021-07-20 |
| 10034393 | Implementing high-speed signaling via dedicated printed circuit-board media | Douglas A. Baska, Daniel M. Dreps, Roger D. Weekly | 2018-07-24 |
| 9972566 | Interconnect array pattern with a 3:1 signal-to-ground ratio | Zhaoqing Chen, Matteo Cocchini, Tingdong Zhou | 2018-05-15 |
| 9773725 | Coreless multi-layer circuit substrate with minimized pad capacitance | Kevin Bills, Mahesh Bohra, Jinwoo Choi, Tae Hong Kim | 2017-09-26 |
| 9646925 | Interconnect array pattern with a 3:1 signal-to-ground ratio | Zhaoqing Chen, Matteo Cocchini, Tingdong Zhou | 2017-05-09 |
| 9600619 | Distribution of power vias in a multi-layer circuit board | Zhaoqing Chen, Matteo Cocchini, Tingdong Zhou | 2017-03-21 |
| 9594865 | Distribution of power vias in a multi-layer circuit board | Zhaoqing Chen, Matteo Cocchini, Tingdong Zhou | 2017-03-14 |
| 9543241 | Interconnect array pattern with a 3:1 signal-to-ground ratio | Zhaoqing Chen, Matteo Cocchini, Tingdong Zhou | 2017-01-10 |
| 9456506 | Packaging for eight-socket one-hop SMP topology | John L. Colbert, Daniel M. Dreps, Paul M. Harvey | 2016-09-27 |
| 9445507 | Packaging for eight-socket one-hop SMP topology | John L. Colbert, Daniel M. Dreps, Paul M. Harvey | 2016-09-13 |
| 9277653 | Through-hole-vias in multi-layer printed circuit boards | Moises Cases, Tae Hong Kim, Nusrat I. Sherali | 2016-03-01 |
| 9232646 | High speed differential wiring in glass ceramic MCMS | Jinwoo Choi, Daniel M. Dreps | 2016-01-05 |
| 9232645 | High speed differential wiring in glass ceramic MCMS | Jinwoo Choi, Daniel M. Dreps | 2016-01-05 |
| 9146735 | Associating workflows with code sections in a document control system | Robert B. Chumbley, Jacob D. Eisinger, Travis M. Grigsby, Christopher M. Laffoon | 2015-09-29 |
| 9060428 | Coreless multi-layer circuit substrate with minimized pad capacitance | Kevin Bills, Mahesh Bohra, Jinwoo Choi, Tae Tong Kim | 2015-06-16 |
| 8975525 | Corles multi-layer circuit substrate with minimized pad capacitance | Kevin Bills, Mahesh Bohra, Jinwoo Choi, Tae Hong Kim | 2015-03-10 |
| 8766107 | Through-hole-vias in multi-layer printed circuit boards | Moises Cases, Tae Hong Kim, Nusrat I. Sherali | 2014-07-01 |
| 8658911 | Through-hole-vias in multi-layer printed circuit boards | Moises Cases, Tae Hong Kim, Nusrat I. Sherali | 2014-02-25 |
| 8619432 | Implementing high-speed signaling via dedicated printed circuit-board media | Douglas A. Baska, Daniel M. Dreps, Roger D. Weekly | 2013-12-31 |
| 8593621 | Testing an optical fiber connection | Kevin Bills, Mahesh Bohra, Hong T. Dang, Roger D. Weekly | 2013-11-26 |
| 8389870 | Coreless multi-layer circuit substrate with minimized pad capacitance | Kevin Bills, Mahesh Bohra, Jinwoo Choi, Tae Hong Kim | 2013-03-05 |
| 8257092 | Redundant clock channel for high reliability connectors | Sungjun Chun, Daniel M. Dreps, Dierk Kaller, Lei Shan | 2012-09-04 |
| 8242384 | Through hole-vias in multi-layer printed circuit boards | Moises Cases, Tae Hong Kim, Nusrat I. Sherali | 2012-08-14 |