Issued Patents All Time
Showing 25 most recent of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163679 | Shallow trench isolation formation without planarization | Siva P. Adusumilli, Steven M. Shank, Anthony K. Stamper | 2018-12-25 |
| 9978849 | SOI-MOSFET gate insulation layer with different thickness | Michel J. Abou-Khalil, Alan B. Botula, Blaine J. Gross, Mark D. Jaffe, Alvin J. Joseph +2 more | 2018-05-22 |
| 9761525 | Multiple back gate transistor | Terence B. Hook, Anthony K. Stamper, Renata Camillo-Castillo | 2017-09-12 |
| 9755015 | Air gaps formed by porous silicon removal | James A. Slinkman | 2017-09-05 |
| 9595579 | Dual shallow trench isolation (STI) structure for field effect transistor (FET) | Natalie B. Feilchenfeld, Max G. Levy, Santosh Sharma, Yun Shi, Michael J. Zierak | 2017-03-14 |
| 9383404 | High resistivity substrate final resistance test structure | Jeffrey P. Gambino, Eric Johnson, Ian McCallum-Cook, Anthony K. Stamper, Michael J. Zierak | 2016-07-05 |
| 9059276 | High voltage laterally diffused metal oxide semiconductor | Natalie B. Feilchenfeld, Theodore Letavic, Santosh Sharma, Yun Shi, Michael J. Zierak | 2015-06-16 |
| 9034712 | Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage | Renata Camillo-Castillo, Erik M. Dahlstrom, Robert J. Gauthier, Jr., Ephrem G. Gebreselasie, Jed H. Rankin +1 more | 2015-05-19 |
| 8946799 | Silicon controlled rectifier with stress-enhanced adjustable trigger voltage | Renata Camillo-Castillo, Erik M. Dahlstrom, Robert J. Gauthier, Jr., Ephrem G. Gebreselasie, Yun Shi +1 more | 2015-02-03 |
| 8921172 | Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure | Xuefeng Liu, Robert M. Rassel, Xiaowei Tian | 2014-12-30 |
| 8828746 | Compensation for a charge in a silicon substrate | Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, James A. Slinkman, Randy L. Wolf | 2014-09-09 |
| 8809155 | Back-end-of-line metal-oxide-semiconductor varactors | John J. Ellis-Monaghan, Michael J. Hauser, Zhong-Xiang He, Xuefeng Liu, Robert M. Rassel +1 more | 2014-08-19 |
| 8796108 | Isolated zener diode, an integrated circuit incorporating multiple instances of the zener diode, a method of forming the zener diode and a design structure for the zener diode | Frederick G. Anderson, Natalie B. Feilchenfeld, David L. Harmon, Yun Shi, Michael J. Zierak | 2014-08-05 |
| 8779476 | Asymmetric wedge JFET, related method and design structure | Xuefeng Liu, Robert M. Rassel, Xiaowei Tian | 2014-07-15 |
| 8754455 | Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure | Xuefeng Liu, Robert M. Rassel, Xiaowei Tian | 2014-06-17 |
| 8748285 | Noble gas implantation region in top silicon layer of semiconductor-on-insulator substrate | Alan B. Botula, William F. Clark, Jr., BethAnn Rainey, Yun Shi, James A. Slinkman | 2014-06-10 |
| 8709903 | Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure | Alan B. Botula, John J. Ellis-Monaghan, Alvin J. Joseph, Max G. Levy, James A. Slinkman +1 more | 2014-04-29 |
| 8698244 | Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method | Alan B. Botula, John J. Ellis-Monaghan, Alvin J. Joseph, Max G. Levy, James A. Slinkman +1 more | 2014-04-15 |
| 8618583 | Junction gate field effect transistor structure having n-channel | Panglijen Candra, Robert M. Rassel, Yun Shi | 2013-12-31 |
| 8598660 | Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltage | Renata Camillo-Castillo, Erik M. Dahlstrom, Robert J. Gauthier, Jr., Ephrem G. Gebreselasie, Jed H. Rankin +1 more | 2013-12-03 |
| 8586423 | Silicon controlled rectifier with stress-enhanced adjustable trigger voltage | Renata Camillo-Castillo, Erik M. Dahlstrom, Robert J. Gauthier, Jr., Ephrem G. Gebreselasie, Yun Shi +1 more | 2013-11-19 |
| 8564067 | Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure | Alan B. Botula, John J. Ellis-Monaghan, Alvin J. Joseph, Max G. Levy, James A. Slinkman +1 more | 2013-10-22 |
| 8536035 | Silicon-on-insulator substrate and method of forming | Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph, Kenneth F. McAvey, Jr., Gerd Pfeiffer | 2013-09-17 |
| 8492866 | Isolated Zener diode | Frederick G. Anderson, Natalie B. Feilchenfeld, David L. Harmon, Yun Shi, Michael J. Zierak | 2013-07-23 |
| 8492294 | Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic suppressing region | Joseph R. Greco, Kevin Munger, Jennifer Robbins, William Savaria, James A. Slinkman +1 more | 2013-07-23 |