Issued Patents All Time
Showing 1–25 of 164 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9024657 | Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller | Alexander E. Andreev, Ivan Pavisic, Alexander Yahontov, Mikhail Udovikhin, Igor Vikhliantsev +3 more | 2015-05-05 |
| 8957398 | Via-configurable high-performance logic block involving transistor chains | Alexander E. Andreev, Sergey Gribok, Phey-Chuin Tan, Chee-Wei Kung | 2015-02-17 |
| 8806227 | Data shredding RAID mode | Mikhail I. Grinchuk, Anatoli Bolotov, Robert D. Waldron | 2014-08-12 |
| 8735857 | Via-configurable high-performance logic block architecture | Alexander E. Andreev, Sergey Gribok | 2014-05-27 |
| 8566769 | Method and apparatus for generating memory models and timing database | Alexandre Andreev, Andrey Nikitin, Igor Vikhliantsev | 2013-10-22 |
| 8516425 | Method and computer program for generating grounded shielding wires for signal wiring | Andrey Nikitin, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto +5 more | 2013-08-20 |
| 8245168 | Method and apparatus for generating memory models and timing database | Alexandre Andreev, Andrey Nikitin, Igor Vikhliantsev | 2012-08-14 |
| 8239813 | Method and apparatus for balancing signal delay skew | Andrey Nikitin, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto +5 more | 2012-08-07 |
| 8132075 | Memory mapping for parallel turbo decoding | Alexander E. Andreev, Anatoli Bolotov | 2012-03-06 |
| 8037432 | Method and apparatus for mapping design memories to integrated circuit layout | Alexandre Andreev, Andrey Nikitin, Ilya V. Neznanov | 2011-10-11 |
| 8035537 | Methods and apparatus for programmable decoding of a plurality of code types | Alexander E. Andreev, Sergey Gribok, Oleg Izyumin, Igor Vikhliantsev, Vojislav Vukovic | 2011-10-11 |
| 8006209 | Method and system for outputting a sequence of commands and data described by a flowchart | Andrey Nikitin, Alexander E. Andreev | 2011-08-23 |
| 7996804 | Signal delay skew reduction system | Andrey Nikitin, Igor Kucherenko, William Lau, Cheng-Gang Kong, Hui-Yin Seto +5 more | 2011-08-09 |
| 7877724 | Decision tree representation of a function | Alexander E. Andreev, Vojislav Vokovic | 2011-01-25 |
| 7856577 | Command language for memory testing | Alexander E. Andreev, Anatoli Bolotov | 2010-12-21 |
| 7788563 | Generation of test sequences during memory built-in self testing of multiple memories | Alexandre Andreev, Anatoli Bolotov | 2010-08-31 |
| 7739471 | High performance tiling for RRAM memory | Alexander E. Andreev, Igor Vikhliantsev | 2010-06-15 |
| 7739575 | Pipelined LDPC arithmetic unit | Alexander E. Andreev, Vojislav Vukovic | 2010-06-15 |
| 7584442 | Method and apparatus for generating memory models and timing database | Alexandre Andreev, Andrey Nikitin, Igor Vikhliantsev | 2009-09-01 |
| 7512918 | Multimode delay analysis for simplifying integrated circuit design timing models | Alexander E. Andreev, Andrey Nikitin | 2009-03-31 |
| 7472358 | Method and system for outputting a sequence of commands and data described by a flowchart | Andrey Nikitin, Alexander E. Andreev | 2008-12-30 |
| 7424687 | Method and apparatus for mapping design memories to integrated circuit layout | Alexandre Andreev, Andrey Nikitin, Ilya V. Neznanov | 2008-09-09 |
| 7415691 | Method and system for outputting a sequence of commands and data described by a flowchart | Alexander E. Andreev, Andrey Nikitin | 2008-08-19 |
| 7415686 | Memory timing model with back-annotating | Alexander E. Andreev, Anatoli Bolotov | 2008-08-19 |
| 7389484 | Method and apparatus for tiling memories in integrated circuit layout | Alexandre Andreev, Andrey Nikitin, Ilya V. Neznanov | 2008-06-17 |