Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12248785 | Instruction length decoding | Sumit Ahuja | 2025-03-11 |
| 10795681 | Instruction length decoding | Sumit Ahuja | 2020-10-06 |
| 10635465 | Apparatuses and methods to prevent execution of a modified instruction | Jamison D. Collins, Jason M. Agron | 2020-04-28 |
| 10545735 | Apparatus and method for efficient call/return emulation using a dual return stack buffer | Jason M. Agron | 2020-01-28 |
| 10409763 | Apparatus and method for efficiently implementing a processor pipeline | Patrick P. Lai, Ethan Schuchman, David Keppel, Denis M. Khartikov, Joshua B. Fryman +7 more | 2019-09-10 |
| 10387159 | Apparatus and method for architectural performance monitoring in binary translation systems | Jason M. Agron, Paul Caprioli, Jiwei Lu, Koichi Yamada | 2019-08-20 |
| 10338927 | Method and apparatus for implementing a dynamic out-of-order processor pipeline | Denis M. Khartikov, Naveen Neelakantam, John H. Kelm | 2019-07-02 |
| 10324724 | Hardware apparatuses and methods to fuse instructions | Patrick P. Lai, Tyler Sondag, Sebastian Winkel, Ethan Schuchman, Jayesh Iyer | 2019-06-18 |
| 10157063 | Instruction and logic for optimization level aware branch prediction | Pedro Marcuello, Alejandro Vicente Martinez, Christos E. Kotselidis, Grigorios Magklis, Fernando Latorre +13 more | 2018-12-18 |
| 10061587 | Instruction and logic for bulk register reclamation | David Keppel, Denis M. Khartikov, Fernando Latorre, Marc Lupon, Grigorios Magklis +2 more | 2018-08-28 |
| 10013326 | Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region | Raul Martinez, Enric Gibert Codina, Pedro Lopez, Marti Torrents Lapuerta, Georgios Tournavitis +14 more | 2018-07-03 |
| 9823938 | Providing deterministic, reproducible, and random sampling in a processor | Girish Venkatasubramanian, Jamison D. Collins, Jason M. Agron | 2017-11-21 |
| 9817642 | Apparatus and method for efficient call/return emulation using a dual return stack buffer | Jason M. Agron | 2017-11-14 |
| 9811341 | Managed instruction cache prefetching | Kyriakos A. Stavrou, Enric Gibert Codina, Josep M. Codina, Crispin Gomez Requena, Antonio Gonzalez +13 more | 2017-11-07 |
| 9710389 | Method and apparatus for memory aliasing detection in an out-of-order instruction execution platform | Oleg Margulis, Sumit Ahuja, Yongjun Park, Vineeth Mekkat, Igor Yanover +2 more | 2017-07-18 |
| 9612840 | Method and apparatus for implementing a dynamic out-of-order processor pipeline | Denis M. Khartikov, Naveen Neelakantam, John H. Kelm | 2017-04-04 |