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Saturation select apparatus and method therefor |
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2003-02-11 |
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Processor having vector processing capability and method for executing a vector instruction in a processor |
Thomas Elmer |
2001-11-27 |
| 6098168 |
System for completing instruction out-of-order which performs target address comparisons prior to dispatch |
Lee Evan Eisen |
2000-08-01 |
| 5872948 |
Processor and method for out-of-order execution of instructions based upon an instruction parameter |
Soummya Mallick, Rajesh B. Patel, Romesh Mangho Jessani |
1999-02-16 |
| 5809323 |
Method and apparatus for executing fixed-point instructions within idle execution units of a superscalar processor |
Lee Evan Eisen, Robert T. Golla, Soummya Mallick, Sung Ho Park, Rajesh B. Patel |
1998-09-15 |
| 5805916 |
Method and apparatus for dynamic allocation of registers for intermediate floating-point results |
Soummya Mallick, Romesh Mangho Jessani |
1998-09-08 |
| 5805475 |
Load-store unit and method of loading and storing single-precision floating-point registers in a double-precision architecture |
Lee Evan Eisen |
1998-09-08 |
| 5805487 |
Method and system for fast determination of sticky and guard bits |
Timothy A. Elliott, Christopher H. Olson |
1998-09-08 |
| 5765191 |
Method for implementing a four-way least recently used (LRU) mechanism in high-performance |
Albert J. Loper, Soummya Mallick, Rajesh Patel |
1998-06-09 |
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Instruction dispatch queue for improved instruction cache to queue timing |
Soummya Mallick, Albert J. Loper |
1998-05-19 |
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Single-precision, floating-point register array for floating-point units performing double-precision operations by emulation |
James Allan Kahle, Tai Dinh Ngo, Aubrey Deene Ogden, Johm Victor Sell |
1998-03-24 |
| 5678016 |
Processor and method for managing execution of an instruction which determine subsequent to dispatch if an instruction is subject to serialization |
Lee Evan Eisen, Robert T. Golla, Christopher H. Olson |
1997-10-14 |
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Method for executing speculative load instructions in high-performance processors |
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1997-03-11 |
| 5375078 |
Arithmetic unit for performing XY+B operation |
David A. Hrusecky |
1994-12-20 |
| 4947359 |
Apparatus and method for prediction of zero arithmetic/logic results |
Stamatis Vassiliadis, Ann E. Huffman, Brice J. Feal, Gerald George Pechanek |
1990-08-07 |
| 4924422 |
Method and apparatus for modified carry-save determination of arithmetic/logic zero results |
Stamatis Vassiliadis, Ann E. Huffman, Brice J. Feal, Gerald George Pechanek |
1990-05-08 |
| 4924424 |
Parity prediction for binary adders with selection |
Stamatis Vassiliadis, Eric M. Schwarz, Brice J. Feal |
1990-05-08 |
| 4914617 |
High performance parallel binary byte adder |
Stamatis Vassiliadis, Eric M. Schwartz |
1990-04-03 |
| 4914579 |
Apparatus for branch prediction for computer instructions |
Stamatis Vassiliadis, Ann E. Huffman, Agnes Y. Ngai |
1990-04-03 |
