Issued Patents All Time
Showing 1–25 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9021236 | Methods and apparatus for storing expanded width instructions in a VLIW memory for deferred execution | Gerald George Pechanek | 2015-04-28 |
| 8671266 | Staging register file for use with multi-stage execution units | Gerald George Pechanek | 2014-03-11 |
| 7962723 | Methods and apparatus storing expanded width instructions in a VLIW memory deferred execution | Gerald George Pechanek | 2011-06-14 |
| 7577824 | Methods and apparatus for storing expanded width instructions in a VLIW memory for deferred execution | Gerald George Pechanek | 2009-08-18 |
| 7006110 | Determining a coverage mask for a pixel | Dan Crisu, Sorin Cotofana, Petri Liuha | 2006-02-28 |
| 6980138 | Method and a system for variable-length decoding, and a device for the localization of codewords | Jari Nikara, Jarmo Takala, Petri Liuha | 2005-12-27 |
| 6405185 | Massively parallel array processor | Gerald George Pechanek, Jose G. Delgado-Frias | 2002-06-11 |
| 6260189 | Compiler-controlled dynamic instruction dispatch in pipelined processors | Dean Batten, Paul D'Arcy, C. John Glossner, Sanjay Jinturkar, Jesse Thilo +1 more | 2001-07-10 |
| 6079010 | Multiple machine view execution in a computer system | Paul D'Arcy, Sanjay Jinturkar, C. John Glossner | 2000-06-20 |
| 6041398 | Massively parallel multiple-folded clustered processor mesh array | Gerald George Pechanek, Jose G. Delgado-Frias | 2000-03-21 |
| 6029240 | Method for processing instructions for parallel execution including storing instruction sequences along with compounding information in cache | Bartholomew Blaner | 2000-02-22 |
| 5784632 | Parallel diagonal-fold array processor | Gerald George Pechanek, Jose G. Delgado-Frias | 1998-07-21 |
| 5732234 | System for obtaining parallel execution of existing instructions in a particulr data processing configuration by compounding rules based on instruction categories | Bartholomew Blaner | 1998-03-24 |
| 5682544 | Massively parallel diagonal-fold tree array processor | Gerald George Pechanek, Jose G. Delgado-Frias | 1997-10-28 |
| 5649135 | Parallel processing system and method using surrogate instructions | Gerald George Pechanek, Clair John Glossner, III, Larry D. Larsen | 1997-07-15 |
| 5649178 | Apparatus and method for storing and initializing branch prediction with selective information transfer | Bartholomew Blaner | 1997-07-15 |
| 5640586 | Scalable parallel group partitioned diagonal-fold switching tree computing apparatus | Gerald George Pechanek, Jose G. Delgado-Frias | 1997-06-17 |
| 5617512 | Triangular scalable neural array processor | Gerald George Pechanek | 1997-04-01 |
| 5613044 | Learning machine synapse processor system apparatus | Gerald George Pechanek, Jose G. Delgado-Frias | 1997-03-18 |
| 5612908 | Processing element for parallel array processor | Gerald George Pechanek, Jose G. Delgado-Frias | 1997-03-18 |
| 5590348 | Status predictor for combined shifter-rotate/merge unit | James E. Phillips, Bartholomew Blaner | 1996-12-31 |
| 5577262 | Parallel array processor interconnections | Gerald George Pechanek, Jose G. Delgado-Fnias | 1996-11-19 |
| 5546336 | Processor using folded array structures for transposition memory and fast cosine transform computation | Gerald George Pechanek | 1996-08-13 |
| RE35311 | Data dependency collapsing hardware apparatus | James E. Phillips, Bartholomew Blaner | 1996-08-06 |
| 5542026 | Triangular scalable neural array processor | Gerald George Pechanek | 1996-07-30 |