Issued Patents All Time
Showing 51–75 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5301341 | Overflow determination for three-operand alus in a scalable compound instruction set machine which compounds two arithmetic instructions | James E. Phillips | 1994-04-05 |
| 5299319 | High performance interlock collapsing SCISM ALU apparatus | James E. Phillips | 1994-03-29 |
| 5295249 | Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel | Bartholomew Blaner | 1994-03-15 |
| 5287467 | Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit | Bartholomew Blaner, Thomas L. Jeremiah, Phillip G. Williams | 1994-02-15 |
| 5251287 | Apparatus and method for neural processing | Gerald George Pechanek | 1993-10-05 |
| 5243688 | Virtual neurocomputer architectures for neural networks | Gerald George Pechanek, Jose G. Delgado-Frias | 1993-09-07 |
| 5214763 | Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism | Bartholomew Blaner | 1993-05-25 |
| 5197135 | Memory management for scalable compound instruction set machines with in-memory compounding | Richard J. Eickemeyer, Bartholomew Blaner | 1993-03-23 |
| 5187679 | Generalized 7/3 counters | Eric M. Schwarz | 1993-02-16 |
| 5148515 | Scalable neural array processor and method | Gerald George Pechanek | 1992-09-15 |
| 5146543 | Scalable neural array processor | Gerald George Pechanek | 1992-09-08 |
| 5146420 | Communicating adder tree system for neural array processor | Gerald George Pechanek | 1992-09-08 |
| 5140545 | High performance divider with a sequence of convergence factors | Josephine A. Boston | 1992-08-18 |
| 5065339 | Orthogonal row-column neural processor | Gerald George Pechanek | 1991-11-12 |
| 5051940 | Data dependency collapsing hardware apparatus | James E. Phillips, Bartholomew Blaner | 1991-09-24 |
| 4947359 | Apparatus and method for prediction of zero arithmetic/logic results | Michael Putrino, Ann E. Huffman, Brice J. Feal, Gerald George Pechanek | 1990-08-07 |
| 4942548 | Parallel adder having removed dependencies | — | 1990-07-17 |
| 4926371 | Two's complement multiplication with a sign magnitude multiplier | Eric M. Schwarz, Baik-Min Sung | 1990-05-15 |
| 4924422 | Method and apparatus for modified carry-save determination of arithmetic/logic zero results | Michael Putrino, Ann E. Huffman, Brice J. Feal, Gerald George Pechanek | 1990-05-08 |
| 4924423 | High speed parity prediction for binary adders using irregular grouping scheme | Eric M. Schwarz | 1990-05-08 |
| 4924424 | Parity prediction for binary adders with selection | Eric M. Schwarz, Michael Putrino, Brice J. Feal | 1990-05-08 |
| 4918639 | Overlapped multiple-bit scanning multiplication system with banded partial product matrix | Eric M. Schwarz | 1990-04-17 |
| 4916652 | Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures | Eric M. Schwarz | 1990-04-10 |
| 4914579 | Apparatus for branch prediction for computer instructions | Michael Putrino, Ann E. Huffman, Agnes Y. Ngai | 1990-04-03 |
| 4914617 | High performance parallel binary byte adder | Michael Putrino, Eric M. Schwartz | 1990-04-03 |