Issued Patents All Time
Showing 26–50 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5517596 | Learning machine synapse processor system apparatus | Gerald George Pechanek, Jose G. Delgado-Frias | 1996-05-14 |
| 5509106 | Triangular scalable neural array processor | Gerald George Pechanek | 1996-04-16 |
| 5504932 | System for executing scalar instructions in parallel based on control bits appended by compounding decoder | Bartholomew Blaner, Thomas L. Jeremiah | 1996-04-02 |
| 5502826 | System and method for obtaining parallel existing instructions in a particular data processing configuration by compounding instructions | Bartholomew Blaner | 1996-03-26 |
| 5500942 | Method of indicating parallel execution compoundability of scalar instructions based on analysis of presumed instructions | Richard J. Eickemeyer | 1996-03-19 |
| 5488707 | Apparatus for predicting overlapped storage operands for move character | James E. Phillips | 1996-01-30 |
| 5483620 | Learning machine synapse processor system apparatus | Gerald George Pechanek, Jose G. Delgado-Frias | 1996-01-09 |
| 5475853 | Cache store of instruction pairs with tags to indicate parallel execution | Bartholomew Blaner | 1995-12-12 |
| 5471628 | Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode | James E. Phillips, Bartholomew Blaner | 1995-11-28 |
| 5465377 | Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel | Bartholomew Blaner | 1995-11-07 |
| 5459844 | Predecode instruction compounding | Richard J. Eickemeyer, Bartholomew Blaner | 1995-10-17 |
| 5448746 | System for comounding instructions in a byte stream prior to fetching and identifying the instructions for execution | Richard J. Eickemeyer | 1995-09-05 |
| 5442767 | Address prediction to avoid address generation interlocks in computer systems | Richard J. Eickemeyer | 1995-08-15 |
| 5426743 | 3-1 Arithmetic logic unit for simultaneous execution of an independent or dependent add/logic instruction pair | James E. Phillips | 1995-06-20 |
| 5423011 | Apparatus for initializing branch prediction information | Bartholomew Blaner | 1995-06-06 |
| 5414797 | Clustering fuzzy expected value system | George Triantafyllos, Walid Kobrosly | 1995-05-09 |
| 5384894 | Fuzzy reasoning database question answering system | Walid Kobrosly, George Triantafyllos | 1995-01-24 |
| 5377336 | Improved method to prefetch load instruction data | Richard J. Eickemeyer | 1994-12-27 |
| 5359718 | Early scalable instruction set machine alu status prediction apparatus | James E. Phillips | 1994-10-25 |
| 5355460 | In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution | Richard J. Eickemeyer, Bartholomew Blaner | 1994-10-11 |
| 5337395 | SPIN: a sequential pipeline neurocomputer | Gerald George Pechanek, Jose G. Delgado-Frias | 1994-08-09 |
| 5329611 | Scalable flow virtual learning neurocomputer | Gerald George Pechanek, Jose G. Delgado-Frias | 1994-07-12 |
| 5325464 | Pyramid learning architecture neurocomputer | Gerald George Pechanek, Jose G. Delgado-Frias | 1994-06-28 |
| 5303176 | High performance array multiplier using four-to-two composite counters | David A. Hrusecky, James E. Phillips | 1994-04-12 |
| 5303356 | System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag | Bartholomew Blaner, Thomas L. Jeremiah | 1994-04-12 |