Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9672033 | Methods and apparatus for transforming, loading, and executing super-set instructions | Gerald George Pechanek | 2017-06-06 |
| 9158547 | Methods and apparatus for scalable array processor interrupt detection and response | Edwin Franklin Barry, Patrick R. Marchand, Gerald George Pechanek | 2015-10-13 |
| 8751772 | Methods and apparatus for scalable array processor interrupt detection and response | Edwin Franklin Barry, Patrick R. Marchand, Gerald George Pechanek | 2014-06-10 |
| 8489858 | Methods and apparatus for scalable array processor interrupt detection and response | Edwin Franklin Barry, Patrick R. Marchand, Gerald George Pechanek | 2013-07-16 |
| 8161267 | Methods and apparatus for scalable array processor interrupt detection and response | Edwin Franklin Barry, Patrick R. Marchand, Gerald George Pechanek | 2012-04-17 |
| 7853779 | Methods and apparatus for scalable array processor interrupt detection and response | Edwin Franklin Barry, Patrick R. Marchand, Gerald George Pechanek | 2010-12-14 |
| 7502451 | Institutional electronic messaging system | Joel Gyllenskog, Randall D. Barber, Albert Pittman, James H. Graham | 2009-03-10 |
| 7493474 | Methods and apparatus for transforming, loading, and executing super-set instructions | Gerald George Pechanek | 2009-02-17 |
| RE40509 | Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture | Gerald George Pechanek, Charles W. Kurak, Jr. | 2008-09-16 |
| 7386710 | Methods and apparatus for scalable array processor interrupt detection and response | Edwin Franklin Barry, Patrick R. Marchand, Gerald George Pechanek | 2008-06-10 |
| 7340591 | Providing parallel operand functions using register file and extra path storage | Gerald George Pechanek, Patrick R. Marchand | 2008-03-04 |
| 6848041 | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions | Gerald George Pechanek, Edwin Franklin Barry, Juan Guillermo Revilla | 2005-01-25 |
| 6842811 | Methods and apparatus for scalable array processor interrupt detection and response | Edwin Frank Barry, Patrick R. Marchand, Gerald George Pechanek | 2005-01-11 |
| 6557094 | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions | Gerald George Pechanek, Edwin Franklin Barry, Juan Guillermo Revilla | 2003-04-29 |
| 6408382 | Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture | Gerald George Pechanek, Charles W. Kurak, Jr. | 2002-06-18 |
| 6397324 | Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file | Edwin Frank Barry, Charles W. Kurak, Jr., Gerald George Pechanek | 2002-05-28 |
| 6321322 | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions | Gerald George Pechanek, Edwin Frank Barry, Juan Guillermo Revilla | 2001-11-20 |
| 6128720 | Distributed processing array with component processors performing customized interpretation of instructions | Gerald George Pechanek, Clair John Glossner, III, Stamatis Vassiliaadis | 2000-10-03 |
| 6101592 | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions | Gerald George Pechanek, Edwin Frank Barry, Juan Guillermo Revilla | 2000-08-08 |
| 5682491 | Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier | Gerald George Pechanek, Clair John Glossner, III, Stamatis Vassiliaadis, Daniel H. McCabe | 1997-10-28 |
| 5659722 | Multiple condition code branching system in a multi-processor environment | Bartholomew Blaner | 1997-08-19 |
| 5659785 | Array processor communication architecture with broadcast processor instructions | Gerald George Pechanek, Clair John Glossner, III, Stamatis Vassiliaadis | 1997-08-19 |
| 5649135 | Parallel processing system and method using surrogate instructions | Gerald George Pechanek, Clair John Glossner, III, Stamatis Vassiliadis | 1997-07-15 |
| 5371872 | Method and apparatus for controlling operation of a cache memory during an interrupt | David W. Nuechterlein, Kim E. O'Donnell, Lee S. Rogers, Thomas Andrew Sartorius, Kenneth D. Schultz +1 more | 1994-12-06 |
| 5115500 | Plural incompatible instruction format decode method and apparatus | — | 1992-05-19 |