Issued Patents All Time
Showing 25 most recent of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8117357 | System core for transferring data between an external device and memory | Gerald George Pechanek, David Strube, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider +6 more | 2012-02-14 |
| 7962667 | System core for transferring data between an external device and memory | Gerald George Pechanek, David Strube, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider +6 more | 2011-06-14 |
| 7024540 | Methods and apparatus for establishing port priority functions in a VLIW processor | Edward A. Wolff, Patrick R. Marchand, David Strube | 2006-04-04 |
| 7017029 | Coprocessor instruction loading from port register based on interrupt vector table indication | — | 2006-03-21 |
| 7010668 | Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution | Thomas L. Drabenstott, Gerald G. Penchanek, Charles W. Kurak, Jr. | 2006-03-07 |
| 6986020 | Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller | Nikos P. Pitsianis, Kevin Coopman | 2006-01-10 |
| 6954842 | Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution | Thomas L. Drabenstott, Gerald George Pechanek, Charles W. Kurak, Jr. | 2005-10-11 |
| 6944683 | Methods and apparatus for providing data transfer control | Edward A. Wolff | 2005-09-13 |
| 6883088 | Methods and apparatus for loading a very long instruction word memory | Gerald George Pechanek | 2005-04-19 |
| 6868490 | Methods and apparatus for providing context switching between software tasks with reconfigurable control | Gerald George Pechanek, David Strube | 2005-03-15 |
| 6865663 | Control processor dynamically loading shadow instruction register associated with memory entry of coprocessor in flexible coupling mode | — | 2005-03-08 |
| 6842811 | Methods and apparatus for scalable array processor interrupt detection and response | Patrick R. Marchand, Gerald George Pechanek, Larry D. Larsen | 2005-01-11 |
| 6834295 | Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller | Nikos P. Pitsianis, Kevin Coopman | 2004-12-21 |
| 6795909 | Methods and apparatus for ManArray PE-PE switch control | Gerald George Pechanek, Thomas L. Drabenstott, Edward A. Wolff, Nikos P. Pitsianis, Grayson Morris | 2004-09-21 |
| 6769056 | Methods and apparatus for manifold array processing | Thomas L. Drabenstott, Gerald George Pechanek, Nikos P. Pitsianis | 2004-07-27 |
| 6760831 | Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution | Thomas L. Drabenstott, Gerald George Pechanek, Charles W. Kurak, Jr. | 2004-07-06 |
| 6748517 | Constructing database representing manifold array architecture instruction set for use in support tool code creation | Gerald George Pechanek, David Strube, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider +6 more | 2004-06-08 |
| 6721822 | Methods and apparatus for providing data transfer control | Edward A. Wolff | 2004-04-13 |
| 6704857 | Methods and apparatus for loading a very long instruction word memory | Gerald George Pechanek | 2004-03-09 |
| 6654870 | Methods and apparatus for establishing port priority functions in a VLIW processor | Edward A. Wolff, Patrick R. Marchand, David Strube | 2003-11-25 |
| 6622234 | Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions | Gerald George Pechanek, David Strube, Edward A. Wolff, Grayson Morris, Carl Donald Busboom +1 more | 2003-09-16 |
| 6581152 | Methods and apparatus for instruction addressing in indirect VLIW processors | Gerald George Pechanek | 2003-06-17 |
| 6470441 | Methods and apparatus for manifold array processing | Gerald George Pechanek, Nikos P. Pitsianis, Thomas L. Drabenstott | 2002-10-22 |
| 6467036 | Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor | Gerald George Pechanek, Juan Guillermo Revilla | 2002-10-15 |
| 6457073 | Methods and apparatus for providing data transfer control | Edward A. Wolff | 2002-09-24 |