Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| RE41703 | Methods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communication | Gerald George Pechanek, Thomas L. Drabenstott, David Strube, Grayson Morris | 2010-09-14 |
| 7568141 | Method and apparatus for testing embedded cores | Sankaran M. Menon, Luis A. Basto, Tien Dinh, Thomas Tomazin | 2009-07-28 |
| 7360059 | Variable width alignment engine for aligning instructions based on transition between buffers | Thomas Tomazin, William C. Anderson, Charles P. Roth, Kayla Chalmers, Ravi P. Singh | 2008-04-15 |
| 7313739 | Method and apparatus for testing embedded cores | Sankaran M. Menon, Luis A. Basto, Tien Dinh, Thomas Tomazin | 2007-12-25 |
| 7272705 | Early exception detection | Ravi P. Singh, Charles P. Roth | 2007-09-18 |
| 7174429 | Method for extending the local memory address space of a processor | Ravi Kolagotla | 2007-02-06 |
| 7124285 | Peak power reduction when updating future file | Ryo Inoue | 2006-10-17 |
| 7082516 | Aligning instructions using a variable width alignment engine having an intelligent buffer refill mechanism | Thomas Tomazin, William C. Anderson, Charles P. Roth, Kayla Chalmers, Ravi P. Singh | 2006-07-25 |
| 7028129 | Method and apparatus for converting an external memory access into a local memory access in a processor core | Minh Tran | 2006-04-11 |
| 6920515 | Early exception detection | Ravi P. Singh, Charles P. Roth | 2005-07-19 |
| 6874078 | Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit | Gerald George Pechanek | 2005-03-29 |
| 6851041 | Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor | Gerald George Pechanek, Edwin Franklin Barry | 2005-02-01 |
| 6848041 | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions | Gerald George Pechanek, Edwin Franklin Barry, Larry D. Larsen | 2005-01-25 |
| 6789187 | Processor reset and instruction fetches | Ravi P. Singh, Charles P. Roth, Ravi Kolagotla | 2004-09-07 |
| 6775766 | Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor | Edwin Franklin Barry, Patrick R. Marchand, Gerald George Pechanek | 2004-08-10 |
| 6606699 | Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit | Gerald George Pechanek | 2003-08-12 |
| 6557094 | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions | Gerald George Pechanek, Edwin Franklin Barry, Larry D. Larsen | 2003-04-29 |
| 6467036 | Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor | Gerald George Pechanek, Edwin Frank Barry | 2002-10-15 |
| 6460120 | Network processor, memory organization and methods | Brian Mitchell Bass, Jean Calvignac, Marco C. Heddes, Piyush C. Patel, Michael S. Siegel +1 more | 2002-10-01 |
| 6446191 | Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication | Gerald George Pechanek, Thomas L. Drabenstott, David Strube, Grayson Morris | 2002-09-03 |
| 6321322 | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions | Gerald George Pechanek, Edwin Frank Barry, Larry D. Larsen | 2001-11-20 |
| 6219776 | Merged array controller and processing element | Gerald George Pechanek | 2001-04-17 |
| 6216223 | Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor | Edwin Frank Barry, Patrick R. Marchand, Gerald George Pechanek | 2001-04-10 |
| 6173389 | Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor | Gerald George Pechanek, Edwin Frank Barry | 2001-01-09 |
| 6151668 | Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication | Gerald George Pechanek, Thomas L. Drabenstott, David Strube, Grayson Morris | 2000-11-21 |