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Semiconductor device including dual damascene interconnections |
Lawrence A. Clevenger |
2007-03-06 |
| 7125790 |
Inclusion of low-k dielectric material between bit lines |
Kia-Seng Low, George C. Feng |
2006-10-24 |
| 6890815 |
Reduced cap layer erosion for borderless contacts |
Johnathan E. Faltermeier, Jeremy K. Stephens, David M. Dobuzinsky, Larry Clevenger, Munir D. Naeem +3 more |
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| 6759332 |
Method for producing dual damascene interconnections and structure produced thereby |
Lawrence A. Clevenger |
2004-07-06 |
| 5795826 |
Method of chemically mechanically polishing an electronic component |
Jeffrey P. Gambino, Mark A. Jaso |
1998-08-18 |
| 5573633 |
Method of chemically mechanically polishing an electronic component |
Jeffrey P. Gambino, Mark A. Jaso |
1996-11-12 |
| 4601779 |
Method of producing a thin silicon-on-insulator layer |
John R. Abernathey, Jerome B. Lasky, Thomas O. Sedgwick, Scott R. Stiffler |
1986-07-22 |
| 4558508 |
Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step |
Wayne Kinney, Charles W. Koburger, III, Jerome B. Lasky, Ronald R. Troutman, Francis R. White |
1985-12-17 |
| 4532700 |
Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer |
Wayne Kinney, Jerome B. Lasky |
1985-08-06 |
| 4389257 |
Fabrication method for high conductivity, void-free polysilicon-silicide integrated circuit electrodes |
Henry J. Geipel, Jr., Ning Hsieh, Charles W. Koburger, III |
1983-06-21 |
