Issued Patents All Time
Showing 25 most recent of 191 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12050798 | Memory migration within a multi-host data processing environment | Derek E. Williams, Guy L. Guthrie, William J. Starke | 2024-07-30 |
| 11860707 | Current prediction-based instruction throttling control | Brian T. Vanderpool, Gerald Mark Grabowski, Michael Stephen Floyd, Matthew A. Cooke | 2024-01-02 |
| 11693776 | Variable protection window extension for a target address of a store-conditional request | Derek E. Williams, Guy L. Guthrie, Hugh Shen | 2023-07-04 |
| 11625087 | Current prediction-based instruction throttling control | Brian T. Vanderpool, Gerald Mark Grabowski, Michael Stephen Floyd, Matthew A. Cooke | 2023-04-11 |
| 11573902 | Controlling issue rates of requests of varying broadcast scopes in a data processing system | Hugh Shen, Guy L. Guthrie, Luke Murray, Alexander Michael Taft, Bernard C. Drerup +1 more | 2023-02-07 |
| 11561900 | Targeting of lateral castouts in a data processing system | Bernard C. Drerup, Guy L. Guthrie, Alexander Michael Taft, Derek E. Williams | 2023-01-24 |
| 11537519 | Marking in-flight requests affected by translation entry invalidation in a data processing system | Derek E. Williams, Guy L. Guthrie, Hugh Shen, David Campbell, Bryan Lloyd +1 more | 2022-12-27 |
| 11449489 | Split transaction coherency protocol in a data processing system | Bernard C. Drerup, Guy L. Guthrie, Michael S. Siegel | 2022-09-20 |
| 11341060 | Multifunction communication interface supporting memory sharing among data processing systems | Michael S. Siegel, William J. Starke, Lakshminarayana B. Arimilli, Kenneth M. Valk, James Francis Mikos +1 more | 2022-05-24 |
| 11269561 | Speculative bank activate dynamic random access memory (DRAM) scheduler | Jie Zheng, Steven R. Carlough, William J. Starke, Stephen J. Powell | 2022-03-08 |
| 11263151 | Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations | David Campbell, Bryan Lloyd, David A. Hrusecky, Kimberly M. Fernsler, Guy L. Guthrie +4 more | 2022-03-01 |
| 11113204 | Translation invalidation in a translation cache serving an accelerator | Bartholomew Blaner, Michael S. Siegel, William J. Starke, Kenneth M. Valk, John D. Irish +1 more | 2021-09-07 |
| 11042325 | Speculative bank activate dynamic random access memory (DRAM) scheduler | Jie Zheng, Steven R. Carlough, William J. Starke, Stephen J. Powell | 2021-06-22 |
| 11030110 | Integrated circuit and data processing system supporting address aliasing in an accelerator | Michael S. Siegel, Bartholomew Blaner, William J. Starke, Derek E. Williams, Kenneth M. Valk +2 more | 2021-06-08 |
| 10884943 | Speculative checkin of ERAT cache entries | Bartholomew Blaner, Jay G. Heaslip, Robert D. Herzl, Jody B. Joyner | 2021-01-05 |
| 10846235 | Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator | Bartholomew Blaner, Michael S. Siegel, William J. Starke, Kenneth M. Valk, John D. Irish +1 more | 2020-11-24 |
| 10831889 | Secure memory implementation for secure execution of virtual machines | William E. Hall, Guerney D. H. Hunt, Ronald Nick Kalla, Jentje Leenstra, Paul Mackerras +1 more | 2020-11-10 |
| 10824952 | Reconfigurable array processor for pattern matching | Bulent Abali, Ganesh Balakrishnan, Bartholomew Blaner, Peter A. Sandon | 2020-11-03 |
| 10824585 | Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elements | Ganesh Balakrishnan, Bartholomew Blaner, John J. Reilly | 2020-11-03 |
| 10824953 | Reconfigurable array processor for pattern matching | Bulent Abali, Ganesh Balakrishnan, Bartholomew Blaner, Peter A. Sandon | 2020-11-03 |
| 10761995 | Integrated circuit and data processing system having a configurable cache directory for an accelerator | Bartholomew Blaner, Michael S. Siegel, William J. Starke, Curtis C. Wollbrink, Kenneth M. Valk +2 more | 2020-09-01 |
| 10713169 | Remote node broadcast of requests in a multinode data processing system | Eric E. Retter, Michael S. Siegel, Derek E. Williams | 2020-07-14 |
| 10691605 | Expedited servicing of store operations in a data processing system | Guy L. Guthrie, Hugh Shen, Derek E. Williams | 2020-06-23 |
| 10671537 | Reducing translation latency within a memory management unit using external caching structures | Guy L. Guthrie, Jody B. Joyner, Ronald Nick Kalla, Michael S. Siegel, Charles D. Wait +1 more | 2020-06-02 |
| 10664398 | Link-level cyclic redundancy check replay for non-blocking coherence flow | Charles F. Marino, William J. Starke, David J. Krolak, Paul Allen Ganfield | 2020-05-26 |