Issued Patents All Time
Showing 25 most recent of 116 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412784 | Recessed vertical interconnects for device miniaturization | Yee Lun Ong, Teong Guan Yew, Bok Eng Cheah | 2025-09-09 |
| 12328816 | Asymmetrical laminated circuit boards for improved electrical performance | Bok Eng Cheah, Tin Poay Chuah, Jenny Shio Yin Ong, Seok Ling Lim | 2025-06-10 |
| 12288740 | Semiconductor package with hybrid mold layers | Bok Eng Cheah, Chia-Chuan Wu, Kooi Chi Ooi | 2025-04-29 |
| 12256487 | Hybrid boards with embedded planes | Bok Eng Cheah, Jenny Shio Yin Ong, Seok Ling Lim, Chin Lee Kuan, Tin Poay Chuah | 2025-03-18 |
| 12218064 | Molded silicon interconnects in bridges for integrated-circuit packages | Bok Eng Cheah, Jenny Shio Yin Ong, Seok Ling Lim, Kooi Chi Ooi | 2025-02-04 |
| 12191281 | Multi-chip package with recessed memory | Bok Eng Cheah, Yang Liang Poh, Seok Ling Lim, Jenny Shio Yin Ong | 2025-01-07 |
| 12183722 | Molded interconnects in bridges for integrated-circuit packages | Jenny Shio Yin Ong, Seok Ling Lim, Bok Eng Cheah | 2024-12-31 |
| 12142570 | Composite bridge die-to-die interconnects for integrated-circuit packages | Bok Eng Cheah, Jenny Shio Yin Ong, Ping Ping Ooi, Seok Ling Lim | 2024-11-12 |
| 12112997 | Micro through-silicon via for transistor density scaling | Bok Eng Cheah, Choong Kooi Chee, Wai Ling Lee, Tat Hin Tan | 2024-10-08 |
| 12080628 | Micro through-silicon via for transistor density scaling | Bok Eng Cheah, Choong Kooi Chee, Wai Ling Lee, Tat Hin Tan | 2024-09-03 |
| 12033953 | Electronic device and crosstalk mitigating substrate | Min Suet Lim, Tin Poay Chuah, Bok Eng Cheah | 2024-07-09 |
| 12002747 | Integrated bridge for die-to-die interconnects | Bok Eng Cheah, Jenny Shio Yin Ong, Seok Ling Lim, Kooi Chi Ooi | 2024-06-04 |
| 11955431 | Interposer structures and methods for 2.5D and 3D packaging | Jenny Shio Yin Ong, Seok Ling Lim, Bok Eng Cheah, Saravanan Sethuraman | 2024-04-09 |
| 11942412 | Interposer with flexible portion | Bok Eng Cheah, Min Suet Lim, Tin Poay Chuah | 2024-03-26 |
| 11887917 | Encapsulated vertical interconnects for high-speed applications and methods of assembling same | Bok Eng Cheah, Kooi Chi Ooi, Yang Liang Poh | 2024-01-30 |
| 11887940 | Integrated circuit packages with conductive element having cavities housing electrically connected embedded components | Seok Ling Lim, Jenny Shio Yin Ong, Bok Eng Cheah | 2024-01-30 |
| 11837458 | Substrate with gradiated dielectric for reducing impedance mismatch | Bok Eng Cheah, Ping Ping Ooi, Kooi Chi Ooi | 2023-12-05 |
| 11798894 | Devices and methods for signal integrity protection technique | Bok Eng Cheah, Khang Choong Yong, Kooi Chi Ooi, Min Suet Lim | 2023-10-24 |
| 11758662 | Three dimensional foldable substrate with vertical side interface | Tin Poay Chuah, Bok Eng Cheah | 2023-09-12 |
| 11676910 | Embedded reference layers for semiconductor package substrates | Bok Eng Cheah, Seok Ling Lim, Jenny Shio Yin Ong, Kooi Chi Ooi | 2023-06-13 |
| 11652026 | Micro through-silicon via for transistor density scaling | Bok Eng Cheah, Choong Kooi Chee, Wai Ling Lee, Tat Hin Tan | 2023-05-16 |
| 11639623 | Micro-hinge for an electronic device | Bok Eng Cheah, Howe Yin Loo, Min Suet Lim, Poh Tat Oh | 2023-05-02 |
| 11574877 | Semiconductor miniaturization through component placement on stepped stiffener | Jenny Shio Yin Ong, Seok Ling Lim, Bok Eng Cheah | 2023-02-07 |
| 11562963 | Stacked semiconductor package and method of forming the same | Chin Lee Kuan, Bok Eng Cheah, Sameer Shekhar, Amit Jain | 2023-01-24 |
| 11562954 | Frame-array interconnects for integrated-circuit packages | Seok Ling Lim, Jenny Shio Yin Ong, Bok Eng Cheah | 2023-01-24 |