Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12422883 | System and a method for aligning a programmable clock or strobe | Soon Chieh Lim, Zhen Peng Chok, Chee Hak Teh, Cheau Nih Tan | 2025-09-23 |
| 12112997 | Micro through-silicon via for transistor density scaling | Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee | 2024-10-08 |
| 12080628 | Micro through-silicon via for transistor density scaling | Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee | 2024-09-03 |
| 11652026 | Micro through-silicon via for transistor density scaling | Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee | 2023-05-16 |
| 11575383 | Clocking system and a method of clock synchronization | Chee Hak Teh, Yu Ying Ong, Wong Ging Yeon Mark, Soong Khim Chew | 2023-02-07 |
| 11398415 | Stacked through-silicon vias for multi-device packages | Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee | 2022-07-26 |
| 11393741 | Micro through-silicon via for transistor density scaling | Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee | 2022-07-19 |
| 11373694 | Generic physical layer providing a unified architecture for interfacing with an external memory device and methods of interfacing with an external memory device | Soon Chieh Lim, Chee Hak Teh | 2022-06-28 |
| 10903142 | Micro through-silicon via for transistor density scaling | Bok Eng Cheah, Choong Kooi Chee, Jackson Chung Peng Kong, Wai Ling Lee | 2021-01-26 |
| 10714163 | Methods for mitigating transistor aging to improve timing margins for memory interface signals | Chee Hak Teh, Tick Sern Loh, Wilfred Wee Kee King, Yu Ying Ong | 2020-07-14 |
| 10333689 | High speed sense amplifier latch with low power rail-to-rail input common mode range | Pankaj Vinayak Dudulwar, Chenchu Punnarao Bandi, Lip Khoon Teh | 2019-06-25 |
| 10223483 | Methods for determining resistive-capacitive component design targets for radio-frequency circuitry | William Walter Fergusson, Chieu Fung Tan | 2019-03-05 |
| 10224911 | Dual signal protocol input/output (I/O) buffer circuit | Choong Kit Wong, Ker Yon Lau, Hsiao-Wei Su, Hoong Chin Ng | 2019-03-05 |
| 10198545 | Systems and methods for extraction of electrical specifications from prelayout simulations | Kian Boon How, Chieu Fung Tan, My Chien Yee | 2019-02-05 |
| 10200046 | High resolution and low power interpolator for delay chain | Chee Seng Leong | 2019-02-05 |
| 10110225 | Integrated circuit with an increased signal bandwidth input/output (I/O) circuit | Ker Yon Lau, Choong Kit Wong | 2018-10-23 |
| 9793888 | Techniques for enabling and disabling transistor legs in an output driver circuit | Yue-Song He, Choong Kit Wong | 2017-10-17 |
| 9443567 | High speed sense amplifier latch with low power rail-to-rail input common mode range | Pankaj Vinayak Dudulwar, Chenchu Punnarao Bandi, Lip Khoon Teh | 2016-09-13 |
| 8239732 | Error correction coding in flash memory devices | Ed Bautista, Bryan W. Hancock, Jackson Huang, Allan Parker | 2012-08-07 |
| 6967532 | Offset-compensated self-biased differential amplifier | — | 2005-11-22 |