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USPTO Patent Rankings Data through Dec 31, 2025
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Allan Parker — 41 Patents

AMD: 26 patents #378 of 9,280Top 5%
SLSpansion Llc.: 15 patents #44 of 769Top 6%
Austin, TX: #646 of 18,064 inventorsTop 4%
Texas: #2,412 of 125,132 inventorsTop 2%
Overall (All Time): #75,001 of 4,157,543Top 2%
41 Patents All Time
Allan Parker has been granted 41 US patents while listed as an inventor at AMD. The first was granted in 1999 and the most recent in September 2014. Allan Parker ranks #75,001 of 4,157,543 US inventors in our database (top 1.8%). Patent records list Allan Parker in Austin, TX, US.

Issued Patents All Time

Showing 1–25 of 41 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8842477 Method, apparatus, and manufacture for flash memory adaptive algorithm 2014-09-23 $4,631,000
8825920 Field upgradable firmware for electronic devices Sean Michael O'Mullan, Bradley Edman Sundahl, Gregory Charles Yancey, Arthur Benjamin Oliver, John Anthony Darilek 2014-09-02 $2,414,000
8638633 Apparatus and method for external charge pump on flash memory module Ali Pourkeramati, Arthur Benjamin Oliver 2014-01-28 $864,000
8542537 Method and apparatus for temperature compensation for programming and erase distributions in a flash memory 2013-09-24 $4,042,000
8498162 Method, apparatus, and manufacture for flash memory write algorithm for fast bits Matthew R. Croft, Pedro SANCHEZ 2013-07-30 $5,323,000
8375262 Field programmable redundant memory for electronic devices Gregory Charles Yancey, Bradley Edman Sundahl, Sean Michael O'Mullan, Arthur Benjamin Oliver, John Anthony Darilek 2013-02-12 $2,724,000
8325531 Memory device 2012-12-04 $1,577,000
8239732 Error correction coding in flash memory devices Tat Hin Tan, Ed Bautista, Bryan W. Hancock, Jackson Huang 2012-08-07 $1,275,000
8117521 Implementation of recycling unused ECC parity bits during flash memory programming Tan Tat Hin, Murni Mohd-Salleh, Edward V. Bautista, Jr. 2012-02-14 $1,872,000
8004888 Flash mirror bit architecture using single program and erase entity as logical cell 2011-08-23 $939,000
7907455 High VT state used as erase condition in trap based nor flash cell design 2011-03-15 $1,649,000
7881105 Quad+bit storage in trap based flash design using single program and erase entity as logical cell 2011-02-01 $1,751,000
7864596 Sector configure registers for a flash device generating multiple virtual ground decoding schemes 2011-01-04 $11,432,000
7804713 EEPROM emulation in flash device 2010-09-28 $1,710,000
7791954 Dynamic erase state in flash device 2010-09-07 $1,192,000
6836432 Partial page programming of multi level flash Glen Lam 2004-12-28 $7,308,000
6785856 Internal self-test circuit for a memory array Joseph Skrovan 2004-08-31 $2,273,000
6728913 Data recycling in memory 2004-04-27 $2,236,000
6707713 Interlaced multi-level memory Joseph Skrovan, Brett Gerhardt 2004-03-16 $3,543,000
6684353 Reliability monitor for a memory array Joseph Skrovan 2004-01-27 $5,673,000
6671207 Piggyback programming with staircase verify for multi-level cell flash memory designs 2003-12-30 $4,545,000
6614683 Ascending staircase read technique for a multilevel cell NAND flash memory device 2003-09-02 $4,831,000
6552929 Piggyback programming using an extended first pulse for multi-level cell flash memory designs 2003-04-22 $3,266,000
6542403 Piggyback programming using voltage control for multi-level cell flash memory designs 2003-04-01 $3,014,000
6538923 Staircase program verify for multi-level cell flash memory designs 2003-03-25 $2,887,000