Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6785856 | Internal self-test circuit for a memory array | Allan Parker | 2004-08-31 |
| 6707713 | Interlaced multi-level memory | Allan Parker, Brett Gerhardt | 2004-03-16 |
| 6684353 | Reliability monitor for a memory array | Allan Parker | 2004-01-27 |
| 6424569 | User selectable cell programming | Allan Parker | 2002-07-23 |
| 6400624 | Configure registers and loads to tailor a multi-level cell flash design | Allan Parker | 2002-06-04 |
| 6112312 | Method for generating functional tests for a microprocessor having several operating modes and features | Allan Parker | 2000-08-29 |
| 6091631 | Program/verify technique for multi-level flash cells enabling different threshold levels to be simultaneously programmed | Joe Kucera | 2000-07-18 |
| 6016554 | Method for event-related functional testing of a microprocessor | Allan Parker | 2000-01-18 |
| 5960457 | Cache coherency test system and methodology for testing cache operation in the presence of an external snoop | Royce K. Presley, Hamilton B. Carter | 1999-09-28 |