Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Program/verify technique for multi-level flash cells enabling different threshold levels to be simultaneously programmed

Program/verify technique for multi-level flash cells enabling different threshold levels to be simultaneously programmed

US Patent 6091631 · Granted Jul 18, 2000

Estimated economic value: $10,732,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Internal self-test circuit for a memory array2004
Interlaced multi-level memory2004
Reliability monitor for a memory array2004
User selectable cell programming2002
Configure registers and loads to tailor a multi-level cell flash design2002
Method for generating functional tests for a microprocessor having several opera2000
Method for event-related functional testing of a microprocessor2000
Cache coherency test system and methodology for testing cache operation in the p1999
Page buffer for a multi-level flash memory with a limited number of latches per 1999