Issued Patents All Time
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6535419 | Mixed mode multi-level indicator | Joseph Kucera | 2003-03-18 |
| 6496410 | Concurrent program reconnaissance with piggyback pulses for multi-level cell flash memory designs | — | 2002-12-17 |
| 6466483 | Piggyback programming using timing control for multi-level cell flash memory designs | — | 2002-10-15 |
| 6452869 | Address broadcasting to a paged memory device to eliminate access latency penalty | — | 2002-09-17 |
| 6424566 | Program reconnaissance to eliminate variations in vt distributions of multi-level cell flash memory designs | — | 2002-07-23 |
| 6424569 | User selectable cell programming | Joseph Skrovan | 2002-07-23 |
| 6418053 | Piggyback programming using graduated steps for multi-level cell flash memory designs | — | 2002-07-09 |
| 6400624 | Configure registers and loads to tailor a multi-level cell flash design | Joseph Skrovan | 2002-06-04 |
| 6343033 | Variable pulse width memory programming | — | 2002-01-29 |
| 6307783 | Descending staircase read technique for a multilevel cell NAND flash memory device | — | 2001-10-23 |
| 6297988 | Mode indicator for multi-level memory | Joseph Kucera | 2001-10-02 |
| 6219276 | Multilevel cell programming | — | 2001-04-17 |
| 6205055 | Dynamic memory cell programming voltage | — | 2001-03-20 |
| 6112312 | Method for generating functional tests for a microprocessor having several operating modes and features | Joseph Skrovan | 2000-08-29 |
| 6016554 | Method for event-related functional testing of a microprocessor | Joseph Skrovan | 2000-01-18 |
| 5973958 | Interlaced storage and sense technique for flash multi-level devices | — | 1999-10-26 |