Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11182166 | Branch prediction throughput by skipping over cachelines without branches | Madhu Saravana Sibi Govindan, Fuzhou Zou, Anhdung Ngo, Wichaya T. Changwatchai, Monika TKACZYK | 2021-11-23 |
| 10402200 | High performance zero bubble conditional branch prediction using micro branch target buffer | James David Dundas, Timothy R Snyder | 2019-09-03 |
| 9286073 | Read-after-write hazard predictor employing confidence and sampling | Paul Kitchin, Brian C. Grayson | 2016-03-15 |
| 9043510 | Hardware streaming unit | Darryl J. Gove, David L. Weaver | 2015-05-26 |
| 8181005 | Hybrid branch prediction device with sparse and dense prediction caches | James David Dundas, Anthony Jarvis | 2012-05-15 |
| 7389402 | Microprocessor including a configurable translation lookaside buffer | Swamy Punyamurtula | 2008-06-17 |
| 7350119 | Compressed encoding for repair | Scott White | 2008-03-25 |
| 7213126 | Method and processor including logic for storing traces within a trace cache | Gregory W. Smaus, Raghuram S. Tupuri | 2007-05-01 |
| 7080170 | Circular buffer using age vectors | Brian D. McMinn, Michael Kevin Ciraula | 2006-07-18 |
| 7024545 | Hybrid branch prediction device with two levels of branch prediction cache | James Roberts | 2006-04-04 |
| 6873184 | Circular buffer using grouping for find first function | Brian D. McMinn, Michael Kevin Ciraula | 2005-03-29 |
| 6854050 | Branch markers for rapidly identifying branch predictions | — | 2005-02-08 |
| 6804799 | Using type bits to track storage of ECC and predecode bits in a level two cache | — | 2004-10-12 |
| 6560740 | Apparatus and method for programmable built-in self-test and self-repair of embedded memory | Timothy J. Wood, Raghuram S. Tupuri | 2003-05-06 |
| 6510508 | Translation lookaside buffer flush filter | Michael T. Clark | 2003-01-21 |
| 6502188 | Dynamic classification of conditional branches in global history branch prediction | James Roberts, Raghuram S. Tupuri | 2002-12-31 |
| 6446189 | Computer system including a novel address translation mechanism | Frederick Daniel Weber, William A. Hughes, William Kurt Lewchuk, Scott White, Michael T. Clark | 2002-09-03 |
| 6415360 | Minimizing self-modifying code checks for uncacheable memory types | William A. Hughes, William Kurt Lewchuk | 2002-07-02 |
| 6405303 | Massively parallel decoding and execution of variable-length instructions | Paul K. Miller | 2002-06-11 |
| 6389512 | Microprocessor configured to detect updates to instructions outstanding within an instruction processing pipeline and computer system including same | Rupaka Mahalingaiah | 2002-05-14 |
| 6259637 | Method and apparatus for built-in self-repair of memory storage arrays | Timothy J. Wood, Raghuram S. Tupuri | 2001-07-10 |
| 6260134 | Fixed shift amount variable length instruction stream pre-decoding for start byte determination based on prefix indicating length vector presuming potential start byte | Syed Faisal Ahmed, Paul K. Miller | 2001-07-10 |
| 6134650 | Apparatus and method for predicting a first scanned instruction as microcode instruction prior to scanning predecode data | Shane Southard, Mauricio Calle | 2000-10-17 |
| 6073217 | Method for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor | Rupaka Mahalingaiah | 2000-06-06 |
| 5742791 | Apparatus for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor | Rupaka Mahalingaiah | 1998-04-21 |